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MC14526BCP
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MC14526BCP数据手册
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© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 5
1 Publication Order Number:
MC14526B/D
MC14526B
Presettable 4−Bit Down
Counters
The MC14526B binary counter is constructed with MOS P−channel
and N−channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Design: Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pb−Free Packages are Available*
MAXIMUM RATINGS
Rating Symbol Value Unit
DC Supply Voltage Range V
DD
0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
,
V
out
−0.5 to V
DD
+ 0.5 V
Input or Output Current
(DC or Transient) per Pin
I
in
, I
out
±10 mA
Power Dissipation per Package (Note 1) P
D
500 mW
Operating Temperature Range T
A
55 to +125 °C
Storage Temperature Range T
stg
65 to +150 °C
Lead Temperature
(8−Second Soldering)
T
L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
SOIC−16 WB
DW SUFFIX
CASE 751G
MARKING
DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
1
1
14526B
AWLYWWG
SOEIAJ−16
F SUFFIX
CASE 966
PDIP−16
P SUFFIX
CASE 648
1
1
MC14526BCP
AWLYYWWG
MC14526B
ALYWG
1
1

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12 页 / 0.32 MByte
ON Semiconductor(安森美)
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