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MC68302CFC16C数据手册
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March 20, 1997 5:12 pm
Page 1 of 13
MC68302 Document
Table 1:
#
Spec
No.
Description
Spec Name
UM
33MHz
Min
33MHz
Max
1 1 Cycle period tcyc
30
2 2,3 Clock pulse width tcl,tch
15
3 5A EXTAL to Clock delay tcd
2
11
4 6 Clock high to FC, address valid tchfcadv
0
27
5 7 Clock high to Address, Data Hi-z tchadz
-
25
6 8 Clock high to Address, FC invalid (Minimum) tchafi
0
-
7 9 Clock high to AS, DS asserted tchsl
3
15
8 11 Address, FC Valid to AS, DS Assert (read)
AS assert (Write)
tafcvsl
8
-
9 12 Clock low to AS, DS negate tclsn
-
15
10 13 AS, DS Negated to Address FC Invalid tshafi
8
-
11 14 AS (and DS read) width asserted tsl
60
-
12 14A DS width asserted, write tdsl
30
-
13 15 AS, DS width negate tsh
30
-
14 16 Clock high to Control Bus Hi-z tchca
-
25
15 17 AS, DS Negated to R/W Invalid tshrh
8
-
16 18 Clock high to R/W hi tchrh
-
15
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68302CFC16C 数据手册

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