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MC9S12A64CPVE
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MC9S12A64CPVE数据手册
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Revision History
Version
Number
Revision
Date
Effective
Date
Author Description of Changes
V01.00
16 NOV
2001
19 NOV
2001
Initial version based on MC9SDP256-2.09 Version.
V01.01
18 FEB
2002
18 FEB
2002
In table 7 I/O Characteristics" of the electrical characteristics
replaced tPULSE withtpign and tpval in lines "Port ... Interrupt Input
Pulse filtered" and "Port ... Interrupt Input Pulse passed"
respectively.
V01.02
6 MAR
2002
6 MAR
2002
Table "Oscillator Characteristics": removed "Oscillator start-up time
from POR or STOP" row
Table "5V I/O Characteristics": Updated
Partial Drive IOH = +–2mA and Full Drive IOH = –10mA
Table "ATD Operating Characteristics": Distinguish I
REF
for 1 and 2
ATD blocks on
Table "ATD Electrical Characteristics": Update C
INS
to 22 pF
Table "Operating Conditions": Changed V
DD
and V
DDPLL
to 2.35 V
(min)
Removed Document number except from Cover Sheet
Updated Table "Document References"
V01.03
4 June
2002
4 June
2002
Table "5V I/O Characteristics" : Corrected Input Capacitance to 6pF
Section: "Device Pinout" (112-pin and 80-pin): added in diagrams
RXCAN0 to PJ6 and TXCAN0 to PJ7
Table "PLL Characteristics": Updated parameters K
1
and f
1
Figure "Basic PLL functional diagram": Inserted XFC pin in diagram
Enhanced section "XFC Component Selection"
Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode
V01.04
4 July
2002
4 July
2002
Added 1L86D to Table "Assigned Part ID numbers"
Corrected MEMSIZ1 value in Table "Memory size registers"
Subsection "Device Memory Map: Removed Flash mapping from
$0000 to $3FFF.
Table "Signal Properties": Added column "Internal Pull Resistor".
Preface Table "Document References": Changed to full naming for
each block.
Table "Interrupt Vector Locations", Column "Local Enable":
Corrected several register and bit names.
V01.05
30 July
2002
30 July
2002
Figure "Recommended PCB Layout for 80QFP: Corrected
VREGEN pin position
Thermal values for junction to board and package
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified mode of Operations chapter
Section "Printed Circuit Board Layout Proposals": added Pierce
Oscillator examples for 112LQFP and 80QFP

MC9S12A64CPVE 数据手册

NXP(恩智浦)
96 页 / 1.69 MByte
NXP(恩智浦)
14 页 / 0.16 MByte
NXP(恩智浦)
126 页 / 1.76 MByte
NXP(恩智浦)
2 页 / 0.09 MByte

MC9S12A64 数据手册

Freescale(飞思卡尔)
Motorola(摩托罗拉)
NXP(恩智浦)
NXP  MC9S12A64CFUE  微控制器, 16位, S12A, 25 MHz, 64 KB, 4 KB, 80 引脚, QFP
NXP(恩智浦)
MC9S12A 系列 16位 25MHz 4KB Ram 闪存 微控制器-LQFP-112
Freescale(飞思卡尔)
S12A/D 系列微控制器装置S12A/D 系列为 16 位微控制器装置 (MCU),也可为低成本系统连接单 8 位宽内存。 该集成 PLL 电路提供功耗和性能灵活性,以满足用户的操作要求。 S12A/D 微控制器装置包括以下标准芯片外围设备; HCS12 CPU 64 K 字节闪存 EEPROM 1 K 字节 EEPROM 4 K 字节 RAM 2 个异步串行通信接口 (SCI) 1 个串行外围接口 (SPI) 8 通道 IC/OC 增强型捕获计时器 2 个 8 通道 10 位模拟至数字转换器 (ADC) 8 通道脉冲宽度调制器 (PWM) 数字字节数据链接控制器 (BDLC) 29 个分离式数字 I/O 通道 20 个分离式数字 I/O 线路 可与 CAN 软件兼容的模块 Byteflight 模块 I2C 总线### S12 微控制器,FreescaleFreescale S12 微控制器是高性能的 16 位设备,用于汽车和工业应用。
Freescale(飞思卡尔)
Freescale(飞思卡尔)
NXP(恩智浦)
NXP(恩智浦)
Freescale(飞思卡尔)
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