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MPC8349EVVAJDB 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
TBGA-672
描述:
微处理器 - MPU 8349 TBGA NO PB W/ ENC
Pictures:
3D模型
符号图
焊盘图
引脚图
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页面导航:
原理图在P234
应用领域在P283
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MPC8349EVVAJDB数据手册
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Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor v
Contents
Paragraph
Number Title
Page
Number
Chapter 1
Overview
1.1 PowerPC Architecture Overview..................................................................................... 1-2
1.1.1 The Levels of the PowerPC Architecture .................................................................... 1-3
1.1.2 Latitude within the Levels of the Architecture............................................................1-4
1.1.3 Features Not Defined by the PowerPC Architecture................................................... 1-4
1.2 The Architectural Models................................................................................................ 1-5
1.2.1 Registers and Programming Model ............................................................................. 1-5
1.2.2 Operand Conventions .................................................................................................. 1-7
1.2.2.1 Byte Ordering .......................................................................................................... 1-7
1.2.2.2 Data Organization in Memory and Data Transfers.................................................. 1-8
1.2.2.3 Floating-Point Conventions..................................................................................... 1-8
1.2.3 Instruction Set and Addressing Modes........................................................................ 1-8
1.2.3.1 Instruction Set..........................................................................................................1-8
1.2.3.2 Calculating Effective Addresses............................................................................ 1-10
1.2.4 Cache Model..............................................................................................................1-10
1.2.5 Interrupt Model.......................................................................................................... 1-10
1.2.6 Memory Management Model (MMU)....................................................................... 1-11
Chapter 2
Register Set
2.1 UISA Register Set............................................................................................................2-1
2.1.1 General-Purpose Registers (GPRs).............................................................................. 2-3
2.1.2 Floating-Point Registers (FPRs).................................................................................. 2-3
2.1.3 Condition Register (CR).............................................................................................. 2-5
2.1.3.1 Condition Register CR0 Field Definition................................................................2-5
2.1.3.2 Condition Register CR1 Field Definition................................................................2-6
2.1.3.3 Condition Register CRn Field—Compare Instruction ............................................2-6
2.1.4 Floating-Point Status and Control Register (FPSCR).................................................. 2-6
2.1.5 XER Register (XER) ................................................................................................... 2-9
2.1.6 Link Register (LR)..................................................................................................... 2-10
2.1.7 Count Register (CTR)................................................................................................ 2-11
2.2 VEA Register Set—Time Base...................................................................................... 2-12
2.2.1 Reading the Time Base.............................................................................................. 2-14
2.2.2 Computing Time of Day from the Time Base ...........................................................2-15
2.3 OEA Register Set........................................................................................................... 2-15
2.3.1 Machine State Register (MSR).................................................................................. 2-18
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