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SI5340C-A-GMR 其他数据使用手册 - Silicon Labs（芯科）
制造商:
Silicon Labs（芯科）
分类:
时钟发生器
封装:
VFQFN-44
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SI5340C-A-GMR数据手册
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Si5347/46/45/44/42/41/40 Errata (A1) Silicon Labs Confidential Page 2
Errata Details
1. Description:
The VCO operating frequency range limits the maximum generated clock output frequency.
Impact:
Frequencies can be generated up to 710 MHz and not 800 MHz as stated in the data sheet.
ClockBuilder Pro currently limits output frequencies to 710 MHz.
Workaround:
There is no workaround for this issue at this time.
Resolution:
This limitation may be fixed in a future revision.
Description:
The oscillator circuit (OSC) may not start up when running the chip at high temperatures. The
ESD protection circuit on XA/XB interacts with an internal regulator for the OSC circuit at start up.
The problem occurs when the junction temperature is above 110 °C.
Impact:
If the chip is powered-up, or a hard or soft reset is performed at high temperatures, the DSPLL
will not be able to achieve lock and output clocks will not be generated.
Workaround:
There is no workaround for this issue. Refer to ClockBuilder Pro’s power dissipation report to help
determine your design’s effective junction temperature.
Resolution:
This issue is fixed in silicon revision B.
2. Description:
The input-to-output delay is not consistent when running the chip at high temperatures. The
problem occurs when the junction temperature is above 110 °C.
Impact:
If the chip is powered-up, or a hard or soft reset is performed at high temperatures, the input-to-
output delay may exceed the data sheet specification.
Workaround:
There is no workaround for this issue.
Resolution:
This erratum will be fixed in a future revision.
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