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器件3D模型￥ 95.017
STM32F303VDT6 其他数据使用手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
32位控制器
封装:
LQFP-100
描述:
STMICROELECTRONICS STM32F303VDT6 微控制器, 32位, 通用, ARM 皮质-M4, 72 MHz, 384 KB, 64 KB, 100 引脚, LQFP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P40Hot
典型应用电路图在P91P92P144
封装尺寸在P152P153P154P155P156P157P158P159P160P161P162P163
型号编码规则在P168P169P171
技术参数、封装参数在P70
电气规格在P68P69P70P71P72P73P74P75P76P77P78P79
导航目录
STM32F303VDT6数据手册
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This is information on a product in full production.
October 2016 DocID026415 Rev 5 1/173
STM32F303xD STM32F303xE
ARM
®
Cortex
®
-M4 32b MCU+FPU, up to 512KB Flash, 80KB SRAM,
FSMC, 4 ADCs, 2 DAC ch., 7 comp, 4 Op-Amp, 2.0-3.6 V
Datasheet - production data
Features
• Core: ARM
®
Cortex
®
-M4 32-bit CPU with
72 MHz FPU, single-cycle multiplication and
HW division, 90 DMIPS (from CCM), DSP
instruction and MPU (memory protection unit)
• Operating conditions:
–V
DD
, V
DDA
voltage range: 2.0 V to 3.6 V
• Memories
– Up to 512 Kbytes of Flash memory
– 64 Kbytes of SRAM, with HW parity check
implemented on the first 32 Kbytes.
– Routine booster: 16 Kbytes of SRAM on
instruction and data bus, with HW parity
check (CCM)
– Flexible memory controller (FSMC) for
static memories, with four Chip Select
• CRC calculation unit
• Reset and supply management
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low-power modes: Sleep, Stop and
Standby
–V
BAT
supply for RTC and backup registers
• Clock management
–4
to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
–
Internal 40 kHz oscillator
• Up to 115 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant
• Interconnect matrix
• 12-channel DMA controller
• Four ADCs 0.20 µs (up to 40 channels)
with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, separate analog
supply from 2.0 to 3.6 V
• Two 12-bit DAC channels with analog supply
from 2.4 to 3.6 V
• Seven ultra-fast rail-to-rail analog comparators
with analog supply from 2.0 to 3.6 V
• Four operational amplifiers that can be used
in
PGA mode, all terminals accessible with
analog supply from 2.4 to 3.6 V
•
Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensor
s
• Up to 14 timers:
– One 32-bit timer and two 16-bit timers with
up to four IC/OC/PWM or pulse counter
and quadrature (incremental) encoder input
– Three 16-bit 6-channel advanced-contro
l
timers, with up to six PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with two IC/OCs, one
OCN/PWM, deadtime generation an
d
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent,
window)
– One SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
• Calendar RTC with Alarm, periodic wakeup
from Stop/Standby
• Communication interfaces
– CAN interface (2.0B Active)
LQFP64
LQF
P100
LQFP144
UFBGA100
(10 × 10 mm)
(14 × 14 mm)
(20 x 20 mm)
(7 x 7 mm)
WLCSP100
(
4.775 x 5.041 mm
)
www.st.com
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