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TMS320C25GBA
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TMS320C25GBA数据手册
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Texas Instruments
TMS320C67x
© 2003 BDTI (www.BDTI.com). All rights reserved.
A BDTI Analysis of the
Contents of this summary include:
• Introduction
• Architecture
• Memory System
• Addressing
• Instruction Set
• BDTI Benchmark Performance:
• Sample Execution Time Results
• Sample Cost-Performance Results
• Sample Energy-Efficiency Results
• Sample Memory Usage Results
• Conclusion
Introduction
The TMS320C67x is a family of 32-
bit floating-point DSPs from Texas
Instruments. The TMS320C67x family
is derived from the TMS320C62x family
of 16-bit fixed-point DSP processors,
and it can execute all TMS320C62x
instructions. In addition, the
TMS320C67x adds supports for IEEE-
754 32-bit single-precision and 64-bit
double-precision floating-point arith-
metic and expands support for 32-bit
fixed-point arithmetic. The
TMS320C67x family targets applica-
tions such as home audio, 3D graphics,
medical imaging, radar, and speech rec-
ognition.
The first TMS320C67x family mem-
bers were announced in April of 1998.
As of mid-2003, the TMS320C67x fam-
ily includes the TMS320C6701,
TMS320C6711, TMS320C6712, and
TMS320C6713. The fastest family
member, the 225 MHz TMS320C6713,
is fabricated in a 0.13-micron process
and uses a 1.26-volt core supply. Other
TMS320C67x family members operate
at speeds ranging from 100 to 200 MHz.
As of mid-2003, prices for
TMS320C67x parts range from under
$15 to over $100 in 10,000-unit quanti-
ties, depending on the family member.
The TMS320C67x is backward-
compatible with the TMS320C62x: the
TMS320C67x can execute
TMS320C62x object code unmodified,
but the TMS320C62x cannot execute all
TMS320C67x instructions. In contrast,
the TMS320C67x is not object-code
compatible with Texas Instruments’ lat-
est generation of the fixed-point
TMS320C6000 architecture, the
TMS320C64x. The TMS320C64x
extends the TMS320C62x instruction set
with instructions that are not supported
by the TMS320C67x.
Architecture
The TMS320C67x contains two
floating-point data paths. Each data path
contains two ALUs, a multiplier, and an
adder/subtractor for address generation.
The ALUs support both integer and
floating-point operations, and the multi-
pliers can perform 16
× 16-bit and
32
× 32-bit integer multiplies as well as
32-bit and 64-bit floating-point multi-
plies.
Each data path contains a register file
of sixteen 32-bit general-purpose regis-
ters. These registers can be used for stor-
ing addresses or data. To support 64-bit
floating-point arithmetic, pairs of adja-
cent registers can be used to hold 64-bit
data.
Memory System
The memory system of the
TMS320C67x implements a modified
Harvard architecture, providing separate
address spaces for instruction and data
memory. The TMS320C67x fetches
instructions using a 32-bit address bus
and 256-bit data bus. Each data path
accesses data using a 32-bit address bus
and a 64-bit data bus. Together, these
data buses can perform two 64-bit loads,
two 32-bit stores, or a 64-bit load and a
32-bit store to or from on-chip memory
per instruction cycle.
The TMS320C67x allows up to two
data move instructions to be executed in
parallel with other instructions.
The TMS320C6701 contains
64 Kbytes of program RAM and
64 Kbytes of data RAM. The program
memory can be configured to act as an
instruction cache.
The TMS320C6711 and
TMS320C6712 use the same two-level
on-chip cache memory architecture as
the fixed-point TMS320C6211. The
TMS320C6711 and TMS320C6712
each contain two 4 Kbyte level-one
caches, one for data and one for instruc-
About BDTI
Founded in 1991, Berkeley Design
Technology, Inc. (BDTI) helps com-
panies develop, select, and use DSP
technology. BDTI provides:
Consulting and Analysis
Independent analysis of processors,
tools, algorithms, and software
Processor benchmarking
Insightful seminars and training
In-depth published reports
Trusted advisory consulting services
Software Development Services
Audio
•Video
Communications
General DSP component libraries
by the staff of
Berkeley Design Technology, Inc.

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