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TMS320F2811PBKS 其他数据使用手册 - TI（德州仪器）
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LQFP-128
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TMS320F2811PBKS数据手册
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Usage Notes and Known Design Exceptions to Functional Specifications
www.ti.com
4
SPRZ193Q–January 2003–Revised February 2017
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Copyright © 2003–2017, Texas Instruments Incorporated
TMS320F281x, TMS320C281x DSPs Silicon Revisions G, F, E, D, C, B, A, 0
4 Usage Notes and Known Design Exceptions to Functional Specifications
4.1 Usage Notes
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
Table 2 and Table 3 show which silicon revision(s) are affected by each usage note.
(1)
Y = Yes
Table 2. List of Usage Notes for F281x
(1)
TITLE
SILICON REVISION(S) AFFECTED
0 A B C D E F G
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write
and Manual CPU Interrupt Mask Clear
Y Y Y Y Y Y Y Y
(1)
Y = Yes
Table 3. List of Usage Notes for C281x
(1)
TITLE
SILICON REVISION(S)
AFFECTED
0 A B
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt
Mask Clear
Y Y Y
4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt
Mask Clear Usage Note
Revision(s) Affected: TMS320F281x: 0, A, B, C, D, E, F and G
TMS320C281x: 0, A, B
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state
that can trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other
interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it
happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be
triggered after the nested interrupt re-enables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is
shown below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
EINT; //Enable nesting in the CPU
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
asm(" NOP"); //Wait for PIEACK to exit the pipeline
EINT; //Enable nesting in the CPU
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