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DSPIC30F2010-20I/SP 产品设计参考手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
DIP-28
描述:
MICROCHIP DSPIC30F2010-20I/SP 芯片, 16位20MIPS DSPIC, SPDIP-28
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DSPIC30F2010-20I/SP数据手册
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若手册格式错乱，请下载阅览PDF原文件
dsPIC30F Family Reference Manual
DS80169E-page 2 2004 Microchip Technology Inc.
1. Page 2-2, Section 2.1 Introduction
On page 2-2, Section 2.1 Introduction, paragraph
5 should be replaced with the following:
The upper 32 Kbytes of the data space memory map can optionally be mapped into program
space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. The program to data space mapping feature lets any instruction access
program space as if it were data space. Furthermore, RAM may be connected to the program
memory bus on devices with an external bus and used to extend the internal data RAM.
2. Page 2-10, Section 2.3.3 Stack Pointer
Overflow
On page 2-10, Section 2.3.3 Stack Pointer Over-
flow, the last sentence in paragraph 2 should be
replaced by the following:
If the contents of the Stack Pointer (W15) are greater than the contents of the SPLIM register by
2 and a push operation is performed, a Stack Error Trap will not occur. The Stack Error Trap will
occur on a subsequent push operation. Thus, for example, if it is desirable to cause a Stack Error
Trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value,
0x1FFE.
3. Page 2-34, Section 2.9.2.5 DO Loop
Restrictions
On page 2-34, Section 2.9.2.5 DO Loop Restric-
tions, the following paragraph and bullets should
be added to the end of this section:
The instruction that is executed two instructions before the last instruction in a DO loop should not
modify any of the following:
•CPU priority level governed by the IPL (SR<7:5>) bits
•Peripheral Interrupt Enable bits governed by the IEC0, IEC1 and IEC2 registers
•Peripheral Interrupt Priority bits governed by the IPC0 through IPC11 registers
If the restrictions above are not followed, the DO loop may execute incorrectly.
4. Page 2-34, Section 2.9.2.5.1 Last
Instruction Restrictions
On page 2-34, Section 2.9.2.5.1 Last Instruction
Restrictions, the following bullet should be added
to the end of the bulleted list:
6. DISI instruction
Note: A Stack Error Trap may be caused by any instruction that uses the contents of the
W15 register to generate an effective address (EA). Thus, if the contents of W15 are
greater than the contents of the SPLIM register by 2, and a CALL instruction is
executed, or if an interrupt occurs, a Stack Error Trap will be generated.
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