Datasheet 搜索 > Intel（英特尔） > EP3C25Q240C8N 数据手册 > EP3C25Q240C8N 产品设计参考手册 2/64 页
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EP3C25Q240C8N 产品设计参考手册 - Intel（英特尔）
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EP3C25Q240C8N数据手册
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Page 2 Device Selection
Cyclone III Design Guidelines August 2013 Altera Corporation
I/O Pin Count, Package Offering and Vertical Migration
The Cyclone III device family offers up to a maximum of 535 user I/O pins.
Depending on your application and board layout, you can select the available
package options:
■ Quad Flat Pack (QFP)
■ FineLine Ball Grid Array (FBGA) with a 1.0 mm ball pitch
■ Ultra FBGA package (UBGA) with an 0.8 mm ball pitch—the smallest in the
Cyclone III device family and saves board space.
Cyclone III devices support vertical migration within the same package. For a given
package, the devices across different densities have the same locations for the power
pins, configuration pins and dedicated pins. This allows future upgrade or changes to
your Cyclone III design without having to change the board layout as you can replace
the Cyclone III device in your board with another Cyclone III device of a different
density.
For best results, you can specify the migration device before compiling your initial
design with the Quartus II software to ensure that only pins that are available in the
same locations on both devices are used in the design for seamless migration to a
larger or smaller device.
1 The number of differential channels may vary across device density.
f For information about the number of user I/O pins and package offerings for the
Cyclone III family across device density, refer to the Cyclone III Device Family Overview
chapter in the Cyclone III Device Handbook.
f For more information about the number of differential channels available for different
densities and packages of the Cyclone III device family, refer to the High-Speed
Differential Interfaces in the Cyclone III Device Family chapter in the Cyclone III Device
Handbook.
Speed Grade
Device speed grade affects the timing closure of the device. Depending on the density
and package, Cyclone III devices are available in three different speed grades:
■ –6 (fastest),
■ –7 and,
■ –8
When migrating to a device of different speed grade, check the timing report from the
timing analysis to ensure that there is no timing violation between different blocks
within the Cyclone III device, between the Cyclone III device and other devices on the
board.
Always design with a sufficient timing margin so that your design can work on
devices of different speed grades. Generally, the difference of one speed grade can
mean a core f
MAX
or I/O performance difference of up to 20%.
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