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EP3C25Q240C8N 产品设计参考手册 - Intel（英特尔）
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EP3C25Q240C8N数据手册
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Early System Planning Page 3
Cyclone III Design GuidelinesAugust 2013 Altera Corporation
Early System Planning
It is important to know your system requirement and what your Cyclone III device
can offer at the early stage of the design cycle.
Early Power Estimation
As FPGAs have increased in logic capacity and performance, the power consumption
must be accurately estimated for appropriate power supply, decoupling and thermal
solution planning. The power supply must be able to provide enough current for the
device operation and the thermal solution must be able to cool the device junction
temperature to within the specification.
Altera provides a power estimation tool called the Early Power Estimator (EPE) to
help you estimate the power consumption of your design during the system planning
phase. The EPE allows you to estimate the power consumption, current drawn from
the power supply and device junction temperature based on the device resources that
you are going to use in your design, along with the information about the ambient
temperature, heat sink, air flow and board thermal model.
You can either enter the design information manually into the spreadsheet or import a
power estimator file of a fully or partially completed design from the Quartus II
software. After importing a file, you can edit some of the input parameters such as the
ambient temperature, airflow, clock frequency and toggle percentage to suit your
system requirements.
f For more information about the EPE and ways generate and import the power
estimator file, refer to the PowerPlay Early Power Estimator User Guide for Cyclone III
FPGAs.
I/O Support
This section discusses the general Cyclone III device I/O support. Before starting with
the I/O planning, take some time to review the support offered by the Cyclone III
I/Os.
Selectable I/O Standards
Cyclone III devices support a wide range of industry I/O standards, including
single-ended, voltage-referenced and differential I/O standards. Selection factors are
driven by performance versus cost. Table 1 simplifies the selection choice for each I/O
signaling type.
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