Datasheet 搜索 > 微处理器 > NXP（恩智浦） > MPC8349EVVAJFB 数据手册 > MPC8349EVVAJFB 产品设计参考手册 6/1180 页
器件3D模型￥ 1520.719
MPC8349EVVAJFB 产品设计参考手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-672
描述:
PowerPC系列 533MHz
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P613Hot
原理图在P84P91P181P226P230P232P238P240P245P246P260P261
封装信息在P83
功能描述在P155P229P237P244P259P265P279P354P364P400P435P463
技术参数、封装参数在P131P162P190P281P290P537P885P1047P1057
应用领域在P100P284P569P892
导航目录
MPC8349EVVAJFB数据手册
Page:
of 1180 Go
若手册格式错乱，请下载阅览PDF原文件
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1
vi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 2
Memory Map
2.1 Internal Memory Mapped Registers ................................................................................ 2-1
2.2 Accessing IMMR Memory From the Local Processor.................................................... 2-1
2.3 Complete IMMR Map ..................................................................................................... 2-1
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-19
3.3 Output Signal States During Reset ................................................................................ 3-19
Chapter 4
Reset, Clocking, and Initialization
4.1 External Signals ...............................................................................................................4-1
4.1.1 Reset Signals................................................................................................................4-1
4.1.2 Clock Signals...............................................................................................................4-3
4.2 Functional Description..................................................................................................... 4-3
4.2.1 Reset Operations.......................................................................................................... 4-3
4.2.1.1 Reset Causes............................................................................................................ 4-4
4.2.1.2 Reset Actions........................................................................................................... 4-4
4.2.2 Power-On Reset Flow.................................................................................................. 4-5
4.2.3 Hard Reset Flow .......................................................................................................... 4-7
4.2.4 Soft Reset Flow............................................................................................................4-8
4.3 Reset Configuration......................................................................................................... 4-8
4.3.1 Reset Configuration Signals ........................................................................................ 4-9
4.3.1.1 Reset Configuration Word Source........................................................................... 4-9
4.3.1.2 CLKIN Division .................................................................................................... 4-10
4.3.1.3 Selecting Reset Configuration Input Signals.........................................................4-10
4.3.2 Reset Configuration Words........................................................................................ 4-11
4.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-11
4.3.2.1.1 System PLL Configuration................................................................................ 4-12
4.3.2.2 Reset Configuration Word High Register (RCWHR)............................................4-14
4.3.2.2.1 PCI Host/Agent Configuration.......................................................................... 4-16
4.3.2.2.2 Boot Memory Space (BMS).............................................................................. 4-16
4.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-17
4.3.2.2.4 Boot ROM Location .......................................................................................... 4-17
4.3.2.2.5 TSEC1 Mode ..................................................................................................... 4-19
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