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TMS320C5535AZHH10 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
BGA-144
描述:
TEXAS INSTRUMENTS TMS320C5535AZHH10 芯片, 数字信号处理器, C55X, 定点, 144BGA
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引脚图在P344P455Hot
典型应用电路图在P285P286
原理图在P37P38P118P138P163P190P204P205P255P256P285P310
功能描述在P52P127P137
应用领域在P558
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TMS320C5535AZHH10数据手册
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3
SPRUH87H–August 2011–Revised April 2016
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Copyright © 2011–2016, Texas Instruments Incorporated
Contents
2.2.2 Radix-2 DIT Butterfly ............................................................................................ 114
2.2.3 Computational Complexity...................................................................................... 115
2.2.4 FFT Graphs....................................................................................................... 116
2.3 DSP Overview Including the FFT Accelerator ........................................................................ 117
2.4 FFT Hardware Accelerator Description................................................................................ 119
2.4.1 Tightly-Coupled Hardware Accelerator ....................................................................... 119
2.4.2 Hardware Butterfly, Double-Stage and Single-Stage Mode................................................ 119
2.4.3 Pipeline and Latency ............................................................................................ 119
2.4.4 Software Control ................................................................................................. 120
2.4.5 Twiddle Factors .................................................................................................. 120
2.4.6 Scaling ............................................................................................................ 120
2.5 HWAFFT Software Interface ............................................................................................ 121
2.5.1 Data Types ....................................................................................................... 121
2.5.2 HWAFFT Functions.............................................................................................. 121
2.5.3 Bit Reverse Function ............................................................................................ 124
2.5.4 Function Descriptions and ROM Locations................................................................... 127
2.5.5 Project Configuration for Calling Functions from ROM ..................................................... 127
2.6 Simple Example to Illustrate the Use of the FFT Accelerator....................................................... 128
2.6.1 1024-Point FFT, Scaling Disabled............................................................................. 128
2.6.2 1024-Point IFFT, Scaling Disabled............................................................................ 129
2.6.3 Graphing FFT Results in CCS4................................................................................ 129
2.7 FFT Benchmarks.......................................................................................................... 130
2.8 Computation of Large (Greater Than 1024-Point) FFTs............................................................. 132
2.8.1 Procedure for Computing Large FFTs ........................................................................ 132
2.8.2 Twiddle Factor Computation ................................................................................... 132
2.8.3 Bit-Reverse Separates Even and Odd Indexes.............................................................. 132
2.8.4 2048-point FFT Source Code .................................................................................. 132
2.9 Appendix A Methods for Aligning the Bit-Reverse Destination Vector............................................. 134
2.9.1 Statically Allocate Buffer at Beginning of Suitable RAM Block ............................................ 134
2.9.2 Use the ALIGN Descriptor to Force log
2
(4 * N) Zeros in the Least Significant Bits..................... 135
2.9.3 Use the DATA_ALIGN Pragma................................................................................ 135
3 Direct Memory Access (DMA) Controller.............................................................................. 136
3.1 Introduction ................................................................................................................ 137
3.1.1 Purpose of the DMA Controller ................................................................................ 137
3.1.2 Key Features of the DMA Controller .......................................................................... 137
3.1.3 Block Diagram of the DMA Controller......................................................................... 138
3.2 DMA Controller Architecture............................................................................................. 139
3.2.1 Clock Control..................................................................................................... 139
3.2.2 Memory Map ..................................................................................................... 140
3.2.3 DMA Channels................................................................................................... 140
3.2.4 Channel Source and Destination Start Addresses .......................................................... 141
3.2.5 Updating Addresses in a Channel............................................................................. 142
3.2.6 Data Burst Capability............................................................................................ 143
3.2.7 Synchronizing Channel Activity to DSP Peripheral Events................................................. 143
3.2.8 Channel Auto-Initialization Capability ......................................................................... 144
3.2.9 Ping-Pong DMA Mode .......................................................................................... 144
3.2.10 Monitoring Channel Activity ................................................................................... 145
3.2.11 Latency in DMA Transfers..................................................................................... 146
3.2.12 Reset Considerations .......................................................................................... 146
3.2.13 Initialization ...................................................................................................... 147
3.2.14 Interrupt Support................................................................................................ 148
3.2.15 Power Management............................................................................................ 148
3.2.16 Emulation Considerations ..................................................................................... 148
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