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ATMEGA32M1-15MZ 用户编程技术手册 - ATMEL（爱特美尔）
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ATMEL（爱特美尔）
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微控制器
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MLF-32
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ATMEGA32M1-15MZ数据手册
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6
ATmega16M1/32M1/64M1 [DATASHEET]
8209ES–AVR–11/2012
2.1 Block diagram
Figure 2-1. Block diagram.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The Atmel ATmega16M1/32M1/64M1 provides the following features: 16/32/64Kbytes of In-System Programmable
Flash with Read-While-Write capabilities, 512B/1K/2Kbytes EEPROM, 1/2/4Kbytes SRAM, 27 general purpose I/O
lines, 32 general purpose working registers, one Motor Power Stage Controller, two flexible Timer/Counters with
compare modes and PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages
with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator, an SPI
serial port, an On-chip Debug system and four software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt
system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, dis-
abling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the
Flash program
memory
Instruction
register
Instruction
decoder
Program
counter
Control lines
32 x 8
general
purpose
registrers
ALU
Status
and control
I/O lines
EEPROM
Data bus 8-bit
Data
SRAM
Direct addressing
Indirect addressing
Interrupt
unit
SPI
unit
Watchdog
timer
Four analog
comparators
DAC
ADC
MPSC
Timer 1
Timer 0
HW LIN/UART
CAN
Current source
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