Datasheet 搜索 > LVDS、M-LVDS、ECL、CML > TI（德州仪器） > DS90C032WGLQMLV 数据手册 > DS90C032WGLQMLV 用户编程技术手册 1/12 页
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DS90C032WGLQMLV 用户编程技术手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
LVDS、M-LVDS、ECL、CML
封装:
SOP
描述:
DS90C032QML LVDS四通道CMOS差分线路接收器 DS90C032QML LVDS Quad CMOS Differential Line Receiver
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DS90C032WGLQMLV数据手册
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DS90C363B
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link -65 MHz
General Description
The DS90C363B transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. At a transmit clock frequency of 65 MHz, 18
bits of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughput is 170 Mbytes/sec. The DS90C363B trans-
mitter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a Falling
edge strobe Receiver (DS90CF366) without any translation
logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
can be applied either before or after the device is
powered.
n Support Spread Spectrum Clocking up to 100kHz
frequency modulation & deviations of
±
2.5% center
spread or −5% down spread.
n "Input Clock Detection" feature will pull all LVDS pairs to
logic low when input clock is missing and when /PD pin
is logic high.
n 18 to 68 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption
<
130 mW (typ)
@
65MHz
Grayscale
n 40% Less Power Dissipation than BiCMOS Alternatives
n Tx Power-down mode
<
37µW (typ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.3 Gbps throughput
n Up to 170 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
n Improved replacement for:
SN75LVDS84, DS90C363A
Block Diagram
DS90C363B
20098601
Order Number DS90C363BMT
See NS Package Number MTD48
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
October 2006
DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
© 2006 National Semiconductor Corporation DS200986 www.national.com
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