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PIC10F202-E/MC
器件3D模型
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PIC10F202-E/MC数据手册
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PIC10F200/202/204/206
DS41228F-page 6 Advance Information 2007-2011 Microchip Technology Inc.
TABLE 3-1: COMMAND MAPPING FOR PIC10F200/202/204/206
3.2.1.1 Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-5.
FIGURE 3-5: LOAD DATA COMMAND (PROGRAM/VERIFY)
3.2.1.2 Read Data From Program Memory
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP
= 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.
FIGURE 3-6: READ DATA FROM PROGRAM MEMORY COMMAND
Command Mapping (MSb … LSb) HEX Data
Load Data for Program Memory xx0010 02h 0, data (14), 0
Read Data from Program Memory xx0100 04h 0, data (14), 0
Increment Address xx0110 06h
Begin Programming xx1000 08h Externally Timed
End Programming xx1110 0Eh
Bulk Erase Program Memory xx1001 09h Internally Timed
TDLY2
1514133216543
THLD1
1
TSET1
21
ICSPCLK
0
ICSPDAT
00
TDLY1
xx
strt_bit
stp_bit
TSET1
-+THLD1
16
MSb X X
LSb
TDLY1
T
SET1
T
HLD1
T
DLY2
12 3 4 56
0
1
0
x
X
12 3 13141516
TDLY3
Input
Output
Input
strt_bit
stp_bit
LSb
MSb
0
ICSPCLK
ICSPDAT

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