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PIC12F509T-I/MC 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
DFN-8
描述:
8位微控制器 -MCU 1.5KB 41B RAM 4MHz
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PIC12F509T-I/MC数据手册
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© 2007 Microchip Technology Inc. Preliminary DS41227E-page 3
PIC12F508/509
3.0 COMMANDS AND
ALGORITHMS
3.1 Program/Verify Mode
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising V
DD pin from
V
IL to VDD. Then raise VPP from VIL to VIHH. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR
pin was initially at VIL). This means
that all I/O are in the Reset state (high-impedance
inputs).
3.1.1 PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x3FF for the PIC12F508 and 0x7FF for the
PIC12F509. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
3.1.2 SERIAL PROGRAM/VERIFY
OPERATION
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (T
SET1)
and hold (T
HLD1) times with respect to the falling edge
of the clock (see Table 6-1).
Commands that do not have data associated with them
are required to wait a minimum of T
DLY2 measured
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait TDLY2
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output
from the PIC12F508/509, the ICSPDAT pin transitions
from the high-impedance input state to the low-imped-
ance output state at the rising edge of the second data
clock (first clock edge after the Start cycle). The
ICSPDAT pin returns to the high-impedance state at
the rising edge of the 16th data clock (first edge of the
Stop cycle). See Figure 3-3.
The commands that are available are described in
Table 3-1.
TABLE 3-1: COMMAND MAPPING FOR PIC12F508/509
VPP
THLD0
ICSPDAT
ICSPCLK
VDD
TPPDP
Note: After every End Programming command,
a delay of T
DIS is required.
Command Mapping (MSb … LSb) Data
Load Data for Program Memory xx00100, data (14), 0
Read Data from Program Memory xx01000, data (14), 0
Increment Address xx0110
Begin Programming xx1000Externally Timed
End Programming xx1110
Bulk Erase Program Memory xx1001Internally Timed
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