Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC16C505-04/P 数据手册 > PIC16C505-04/P 用户编程技术手册 5/14 页
器件3D模型￥ 17.963
PIC16C505-04/P 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
PDIP-14
描述:
MICROCHIP PIC16C505-04/P 微控制器, 8位, 一次性可编程, PIC16C5xx, 4 MHz, 1.5 KB, 72 Byte, 14 引脚, DIP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P1Hot
电气规格在P10
导航目录
PIC16C505-04/P数据手册
Page:
of 14 Go
若手册格式错乱，请下载阅览PDF原文件
2001 Microchip Technology Inc. DS30603B-page 5
PIC16C50X
2.4 Program/Verify Mode
The Program/Verify mode is entered by holding pins
RB1 and RB0 low, while raising MCLR
pin from VIL to
V
IHH (high voltage). Once in this mode, the user pro-
gram memory and the configuration memory can be
accessed and programmed in serial fashion. The mode
of operation is serial, and the memory that is accessed
is the user program memory. RB0 and RB1 are Schmitt
Trigger inputs in this mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the RESET
state (the MCLR
pin was initially at VIL). This means
that all I/O are in the RESET state (High impedance
inputs).
2.4.1 PROGRAM/VERIFY OPERATION
The RB1 pin is used as a clock input pin, and the RB0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB1) is cycled six times. Each command bit
is latched on the falling edge of the clock with the least
significant bit (LSb) of the command being input first.
The data on pin RB0 is required to have a minimum
setup and hold time (see AC/DC specs), with respect to
the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
have a minimum delay of 1µs between the command
and the data. After this delay the clock pin is cycled 16
times with the first cycle being a START bit and the last
cycle being a STOP bit. Data is also input and output
LSb first. Therefore, during a read operation, the LSb
will be transmitted onto pin RB0 on the rising edge of
the second cycle, and during a load operation, the LSb
will be latched on the falling edge of the second cycle.
A minimum 1µs delay is also specified between con-
secutive commands.
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
The commands that are available are listed in Table 2-1.
Note: The MCLR pin should be raised from VIL to
V
IHH within 9 ms of VDD rise. This is to
ensure that the device does not have the
PC incremented while in valid operation
range.
TABLE 2-1: COMMAND MAPPING
Command Mapping (MSb ... LSb) Data
Load Data
000010
0, data(14), 0
Read Data
000100
0, data(14), 0
Increment Address
000110
Begin programming
001000
End Programming
001110
Note: The clock must be disabled during in-circuit programming.
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
