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PIC18F252-I/SP 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
DIP-28
描述:
MICROCHIP PIC18F252-I/SP 微控制器, 8位, 闪存, PIC18Fxx2, 40 MHz, 32 KB, 1.5 KB, 28 引脚, NDIP
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PIC18F252-I/SP数据手册
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2010 Microchip Technology Inc. DS39576C-page 5
PIC18FXX2/XX8
2.4 High Level Overview of the
Programming Process
Figure 2-5 shows the high level overview of the pro-
gramming process. First, a bulk erase is performed.
Next, the code memory, ID locations, and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the configuration bits are then
programmed and verified.
2.5 Entering High Voltage ICSP
Program/Verify Mode
The High Voltage ICSP Program/Verify mode is
entered by holding SCLK and SDATA low, and then
raising MCLR/VPP to VIHH (high voltage). Once in this
mode, the code memory, data EEPROM, ID locations,
and configuration bits can be accessed and
programmed in serial fashion.
The sequence that enters the device into the Program-
ming/Verify mode places all unused I/Os in the high
impedance state.
2.5.1 ENTERING LOW VOLTAGE ICSP
PROGRAM/VERIFY MODE
When the LVP configuration bit is ‘1’ (see Section 5.3),
the Low Voltage ICSP mode is enabled. Low Voltage
ICSP Program/Verify mode is entered by holding SCLK
and SDATA low, placing a logic high on PGM, and then
raising MCLR
/VPP to VIH. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the Program-
ming/Verify mode places all unused I/Os in the high
impedance state.
FIGURE 2-4: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
FIGURE 2-5: HIGH LEVEL
PROGRAMMING FLOW
FIGURE 2-6: ENTERING LOW VOLTAGE
PROGRAM/ VERIFY MODE
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
VDD
D110
P13
Start
Program Memory
Program IDs
Program Data
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
PGM
P15
VDD
VIH
VIH
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