Datasheet 搜索 > 微控制器 > ST Microelectronics（意法半导体） > STM32F102C6T6A 数据手册 > STM32F102C6T6A 开发手册 5/10 页
器件3D模型￥ 8.393
STM32F102C6T6A 开发手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
微控制器
封装:
LQFP-48
描述:
STM32F102 系列微处理器，STMicroelectronicsST 的 STM32F102 MCU 系列 ARM Cortex™ M3、32 位 RISC 内核运行频率高达 48MHz，带高达 128 KB 的高速闪存、高达 16 KB 的 SRAM 以及增强型外设。 ARM™ 处理器 STM32 F102 32 位微控制器具有一个通信接口；计时器；ADC 和 DAC。 STM32 系列 ARM Cortex-M3 32 位闪存产品系列以低功率、低电压运行，并结合了带实时功能的高性能，可以在 STMicroelectronics STM32 平台上运行。 微控制器可用于如应用控制、消费者电器用具、PC 外设、手持设备、HVAC 及其他许多应用领域。 48 MHz CPU，带 USB FS 电源：2 V 至 3.6 V 通信接口：I2C、SPI、USART 12 位 ADC；16 位计时器 温度范围：-40 至 +85 °C ### STM32F1 系列 32 位 ARM® Cortex®-M3 微控制器，STMicroelectronics32 位闪存微控制器的 STM32 系列基于 ARM Cortex™ M3 核心的突破 - 为嵌入式应用特别开发的核心。 STM32 系列得益于 Cortex-M3 体系结构增强功能，包括为传达改进性能而设置的 Thumb-2 指令，带更好的编码密度，对中断更快的反应，所有的均和领先的工业功耗相接合。出色的实时表现 卓越功效 卓越的和新型的外围设备 最大程度的集成 跨族引脚，外围设备和软件兼容性展开
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
应用领域在P10
导航目录
STM32F102C6T6A数据手册
Page:
of 10 Go
若手册格式错乱，请下载阅览PDF原文件
AN3109 FIFO emulation with DMA
Doc ID 16795 Rev 1 5/10
1.2 RAM FIFO emulation in STM32 microcontrollers
The DMA capability of STM32 microcontrollers greatly simplifies the FIFO implementation.
DMA is an efficient way of implementing RAM FIFO based on the principle described in
Section 1.1: FIFO overview.
DMA features that simplify the FIFO implementation:
● Independent source and destination transfer sizes (byte, half-word, word), to emulate
packing and unpacking
● Support for circular buffer management
● Access to Flash memory, SRAM, APB1, APB2 and AHB peripherals as source and
destination
● Programmable number of data items to be transferred: up to 65536
All these features concur to minimize the software overhead associated with data storage.
The DMA memory increment mode is very useful because, with it, the data pointer can be
automatically incremented.
Here, the DMA buffer emulates the FIFO buffer. The write buffer pointer (DMA pointer) is
automatically incremented and the DMA count is automatically decremented when the FIFO
is filled.
The read buffer locations are incremented by software every time data are retrieved from the
FIFO buffer.
1.3 FIFO software implementation
1.3.1 Implementation
This example describes the basic architecture of a circular buffer FIFO for a communication
peripheral. The USART is provided as an example.
Data are received and stored into the DMA circular buffer, where they remain until they are
removed and manipulated.
The transmitter transmits n data items using DMA. The message length (n) is known in
advance.
The receiver receives m (potentially unknown) data items using DMA. It is still possible to
get the peripheral’s RXNE interrupt even when using DMA. In fact, the interrupt from the
peripheral emulates the FIFO nonempty interrupt.
For reception:
● There is no need to clear the RXNE flag in the receive interrupt routine, as it was
automatically cleared by the DMA data read operation. However, the interrupt remains
pending in the NVIC (even though the RXNE flag is no longer set).
● Two buffers are used:
– RxBuffer2: it is defined as the DMA memory base address from which data will be
read. This buffer emulates the FIFO buffer.
– RxBuffer2_SW: it is a software buffer used, inside the receive interrupt routine, to
transfer the received data from the FIFO. It is the final data storage destination.
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
