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STM32F102C6T6A 开发手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
微控制器
封装:
LQFP-48
描述:
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STM32F102C6T6A数据手册
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FIFO emulation with DMA AN3109
6/10 Doc ID 16795 Rev 1
● Inside the receive interrupt routine, the RAM address pointer/count of the DMA are
used to indicate:
– how many data bytes are available in the FIFO buffer (RxBuffer2) to be transferred
to the final data storage buffer (RxBuffer2_SW)
– which is the current FIFO location of the data
Incoming data are temporarily stored into the FIFO buffer, when the receive DMA requests
are serviced. Data retrieval from the FIFO and/or processing is/are triggered by the receive
interrupts.
In the firmware example provided with this application note, USART1 or USART3
(depending on the STMicroelectronics evaluation board used) serves as the transmitter.
USART2 serves as the receiver using DMA and interrupts. The transmitter (USART1 or
USART3) transmits 250 data bytes to USART2.
The receive DMA buffer length is equal to 200 and is defined as circular.
When the USART2 receive interrupt is triggered, the FIFO is read and the RxBuffer2_SW
buffer is filled based on the current DMA pointer/count.
1.3.2 Advantages
DMA is an efficient way of implementing a configurable FIFO for the different communication
peripherals.
This emulated FIFO implementation is needed in reception using DMA when the data length
is not known in advance. There are two major cases:
● A continuous flow of data is received and the incoming data flow can be processed by
the application as soon as it is received. This case could be directly implemented using
the USART receive interrupt. However, FIFO emulation has the major advantage of
reducing the real-time/latency requirements on the USART interrupt. Once the data are
present in the FIFO buffer, they can be processed by software when the CPU is free of
other higher-priority tasks.
● The end of the data block can be determined by the data content —e.g. the software
may check for the presence of an SOF character in the received flow. Another way
consists in detecting the end of the data block through a pause (long interval without
any data reception) in the data flow. This particular case is discussed in Section 1.3:
FIFO software implementation.
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