Datasheet 搜索 > 运算放大器 > TI（德州仪器） > LM7171BIMX/NOPB 数据手册 > LM7171BIMX/NOPB 其他数据使用手册 4/49 页
器件3D模型￥ 22.377
LM7171BIMX/NOPB 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
运算放大器
封装:
SOIC-8
描述:
运算放大器, 高速, 1个放大器, 220 MHz, 4100 V/µs, 5.5V 至 36V, SOIC, 8 引脚
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P3P4P5Hot
典型应用电路图在P25P26
原理图在P12P25
封装尺寸在P41P43P44P45
焊盘布局在P46
标记信息在P41
封装信息在P41P42P43P44
技术参数、封装参数在P6
应用领域在P30
电气规格在P6P7P8P9
导航目录
LM7171BIMX/NOPB数据手册
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4
LM5046
ZHCS581H –FEBRUARY 2011–REVISED NOVEMBER 2014
www.ti.com.cn
Copyright © 2011–2014, Texas Instruments Incorporated
Pin Functions
PIN
I/O DESCRIPTION APPLICATION INFORMATION
NAME
38 PIN
TSSOP
NO.
28 PIN
TSSOP
NO.
WQFN
NO.
UVLO 1 1 25 I
Line
Undervoltage
Lockout
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO
reaches the 0.4 V threshold the VCC and REF regulators
are enabled. At the 1.25 V threshold, the SS pin is released
and the controller enters the active mode. Hysteresis is set
by an internal current sink that pulls 20 µA from the external
resistor divider.
OVP/O
TP
2 2 26 I
Overvoltage
Protection
An external voltage divider from the input power supply sets
the shutdown level during an over-voltage condition.
Alternatively, an external NTC thermistor voltage divider can
be used to set the shutdown temperature. The threshold is
1.25 V. Hysteresis is set by an internal current that sources
20 µA of current into the external resistor divider.
RAMP 4 3 27 I
Input to PWM
Comparator
Modulation ramp for the PWM comparator. This ramp can
be a signal representative of the primary current (current
mode) or proportional to the input voltage (feed-forward
voltage mode). This pin is reset to GND at the end of every
cycle.
CS 6 4 28 I
Current Sense
Input
If CS exceeds 750 mV the PWM output pulse will be
terminated, entering cycle-by-cycle current limit. An internal
switch holds CS low for 40 nS after either output switches
high to blank leading edge transients.
SLOPE 7 5 1 O
Slope
Compensation
Current
A ramping current source from 0 to 100 µA is provided for
slope compensation in current mode control. This pin can be
connected through an appropriate resistor to the CS pin to
provide slope compensation. If slope compensation is not
required, SLOPE must be tied to ground.
COMP 8 6 2 I
Input to the Pulse
Width Modulator
An external opto-coupler connected to the COMP pin
sources current into an internal NPN current mirror. The
PWM duty cycle is at maximum with zero input current,
while 1 mA reduces the duty cycle to zero. The current
mirror improves the frequency response by reducing the AC
voltage across the opto-coupler.
REF 9 7 3 O
Output of a 5V
reference
Maximum output current is 15 mA. Locally decouple with a
0.1µF capacitor.
RT/SY
NC
10 8 4 I
Oscillator
Frequency
Control and
Frequency
Synchronization
The resistance connected between RT and AGND sets the
oscillator frequency. Synchronization is achieved by AC
coupling a pulse to the RT/SYNC pin that raises the voltage
at least 1.5 V above the 2 V nominal bias level.
AGND 11 9 5 I Analog Ground Connect directly to the Power Ground.
RD1 12 10 6 I
Passive to Active
Delay
The resistance connected between RD1 and AGND sets the
delay from the falling edge of HO1/SR1 or LO1/SR2 and the
rising edge of LO1 or HO1 respectively.
RD2 13 11 7 I
Active to Passive
Delay
The resistance connected between RD2 and AGND sets the
delay from the falling edge of LO2 or HO2 and the rising
edge of HO2 or LO2 respectively.
RES 16 12 8 I Restart Timer
Whenever the CS pin exceeds the 750 mV cycle-by-cycle
current limit threshold, 30 µA current is sourced into the
RES capacitor for the remainder of the PWM cycle. If the
RES capacitor voltage reaches 1.0 V, the SS capacitor is
discharged to disable the HO1, HO2, LO1, LO2 and SR1,
SR2 outputs. The SS pin is held low until the voltage on the
RES capacitor has been ramped between 2 V and 4 V eight
times by 10 µA charge and 5 µA discharge currents. After
the delay sequence, the SS capacitor is released to initiate
a normal start-up sequence.
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