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MSP430F2617TZQW 其他数据使用手册 - TI（德州仪器）
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MSP430F2617TZQW数据手册
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Detailed Bug Description
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3 Detailed Bug Description
ADC18 ADC12 Module
Function Incorrect conversion result in extended sample mode
Description The ADC12 conversion result can be incorrect if the extended sample mode is selected
(SHP = 0), the conversion clock is not the internal ADC12 oscillator (ADC12SSEL > 0),
and one of the following two conditions is true:
- The extended sample input signal SHI is asynchronous to the clock source used for
ADC12CLK and the undivided ADC12 input clock frequency exceeds 3.15 MHz.
or
- The extended sample input signal SHI is synchronous to the clock source used for
ADC12CLK and the undivided ADC12 input clock frequency exceeds 6.3 MHz.
Workaround - Use the pulse sample mode (SHP = 1).
or
- Use the ADC12 internal oscillator as the ADC12 clock source.
or
- Limit the undivided ADC12 input clock frequency to 3.15 MHz.
or
- Use the same clock source (such as ACLK or SMCLK) to derive both SHI and
ADC12CLK, to achieve synchronous operation, and also limit the undivided ADC12 input
clock frequency to 6.3 MHz.
ADC19 ADC12 Module
Function Sample start in extended pulse mode
Description When operating in extended pulse mode, if ADC12SC is set in the same instruction as
the first setting of ENC, a sample is not started (that is, the ADC12SC bit has no effect).
Instead, ENC must be set at least one instruction prior to the first occurrence of
ADC12SC being set.
Workaround Set ENC in a separate instruction prior to setting ADC12SC.
ADC25 ADC12 Module
Function Write to ADC12CTL0 triggers ADC12 when CONSEQ = 00
Description If ADC conversions are triggered by the Timer_B module and the ADC12 is in single-
channel single-conversion mode (CONSEQ = 00), ADC sampling is enabled by write
access to any bit(s) in the ADC12CTL0 register. This is contrary to the expected
behavior that only the ADC12 enable conversion bit (ADC12ENC) triggers a new ADC12
sample.
Workaround When operating the ADC12 in CONSEQ=00 and a Timer_B output is selected as the
sample and hold source, temporarily clear the ADC12ENC bit before writing to other bits
in the ADC12CTL0 register. The following capture trigger can then be re-enabled by
setting ADC12ENC = 1.
4
MSP430F2617 Device Erratasheet SLAZ187I–October 2012–Revised April 2015
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