Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC18F45K20-I/P 数据手册 > PIC18F45K20-I/P 其他数据使用手册 4/18 页
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PIC18F45K20-I/P 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
PDIP-40
描述:
MICROCHIP PIC18F45K20-I/P 微控制器, 8位, 闪存, AEC-Q100, PIC18FxxKxx, 64 MHz, 32 KB, 1.5 KB, 40 引脚, DIP
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符号图
焊盘图
引脚图
产品图
页面导航:
封装信息在P12P13
电气规格在P14
导航目录
PIC18F45K20-I/P数据手册
Page:
of 18 Go
若手册格式错乱，请下载阅览PDF原文件
PIC18F24K20/25K20/44K20/45K20
DS80000425K-page 4 2008-2013 Microchip Technology Inc.
Silicon Errata Issues
1. Module: ECCP
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.
Affected Silicon Revisions
2. Module: ECCP
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of the bridge.
Work around
None.
Affected Silicon Revisions
3. Module: MSSP SPI
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to zero
immediately before writing to SSPBUF.
Option 2: Turn Timer2 off and clear TMR2 before
writing SSPBUF. Enable TMR2 after
SSPBUF is written.
Affected Silicon Revisions
4. Module: MSSP I
2
C™
Slew rate is slower than I
2
C specifications when
the SLRCON<2> bit is set.
Work around
Clear SLRCON<2> bit when using the I
2
C
peripheral.
Affected Silicon Revisions
5. Module: ADC
Offset error is 3 LSb typical, 7 LSb maximum,
including an acquisition time-dependent
component (~2 LSb).
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversion is
greater than 100 ms then take two ADC
conversions and discard the first.
Affected Silicon Revisions
6. Module: MSSP I
2
C
If a new address byte is received while the BF flag
is set, the SSPOV bit is properly set and an ACK is
not properly generated. If only the SSPOV bit is set
(BF flag was cleared) and a matching address is
clocked in, that received byte will be improperly
loaded into the SSPBUF register and an ACK will
be improperly generated.
Work around
None.
Affected Silicon Revisions
Note 1: This document summarizes all silicon
errata issues from all specified revisions
of silicon.
2: Shaded cells in this section indicate latest
silicon in production.
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
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