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PIC18F67K22-I/MR 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
QFN-64
描述:
MICROCHIP PIC18F67K22-I/MR 微控制器, 8位, 闪存, PIC18FxxKxx, 64 MHz, 128 KB, 4 KB, 64 引脚, QFN
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PIC18F67K22-I/MR数据手册
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2010-2015 Microchip Technology Inc. DS80000507L-page 3
PIC18F87K22 FAMILY
Silicon Errata Issues
1. Module: Analog-to-Digital Converter
(A/D)
1.1 The A/D will not meet the Microchip standard
A/D specification. The A/D may be usable if
tested at the user end. The possible issues are
high offset error, high DNL error and multiple
missing codes. The A/D can be tested and used
for relative measurements.
A/D Offset
The A/D may have a high offset error, up to a
maximum of 50 LSB; it can be used if the A/D is
calibrated for the offset.
Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect the A/D +ve
input to ground and take the A/D reading. This
will be the offset of the device and can be used
to compensate for the subsequent A/D readings
on the actual inputs.
Affected Silicon Revisions
1.2 The A/D will meet the Microchip standard A/D
specification when used as a 10-bit A/D. When
used as a 12-bit A/D, the possible issues include
high offset error (up to a maximum of ±25 LSBs
at 25°C, ±30 LSBs at 85°C, 125°C and -40°C),
high DNL error (up to a maximum of ±4 LSBs)
and multiple missing codes (up to a maximum of
20). Users should evaluate the 12-bit A/D
performance in their application using the
suggested work around below. See Table 3 for
guidance specifications.
A/D Offset
:
The A/D may have high offset error, up to a
maximum of ±25 LSBs at 25°C, ±30 LSBs at
85°C, 125°C and -40°C; it can be used if the A/D
is calibrated for the offset.
Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect A/D +ve input to
ground and take the A/D reading. This will be the
offset of the device and can be used to
compensate for the subsequent A/D readings
on the actual inputs.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B5, C6).
A3 B1 B3 B5 C1 C3 C5 C6
X
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