Datasheet 搜索 > DSP数字信号处理器 > TI（德州仪器） > TMS320C6455BCTZ8 数据手册 > TMS320C6455BCTZ8 其他数据使用手册 3/82 页
￥ 1410.641
TMS320C6455BCTZ8 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
BFBGA-697
描述:
定点数字信号处理器 697-FCBGA 0 to 90
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P9
技术参数、封装参数在P8P9P10P11P12P13P15P16P17P18P19P20
应用领域在P35P82
导航目录
TMS320C6455BCTZ8数据手册
Page:
of 82 Go
若手册格式错乱，请下载阅览PDF原文件
Contents
1 Introduction ........................................................................................................................ 5
1.1 Device and Development-Support Tool Nomenclature ............................................................. 5
1.2 Package Symbolization and Revision Identification ................................................................ 6
2 Silicon Revision 3.1 Usage Notes and Known Design Exceptions to Functional
Specifications ..................................................................................................................... 8
2.1 Usage Notes for Silicon Revision 3.1 ................................................................................. 8
2.1.1 DDR2 Memory Controller: Chip Enable Pin Remains Low, Always Active .......................... 8
2.1.2 PLL: Hosts Should Not Access the DSP While PLL Registers are Being Configured ............. 8
2.1.3 EMIFA: Chip Enable Pin Must Be Used to Interface With Devices Connected to EMIFA ......... 8
2.1.4 EMIFA: EDMA FIFO Addressing Mode Should Not Be Used When Reading from EMIFA ....... 9
2.1.5 HPI: Certain HPIC Register Bits Will Reset to Default Value Only With Power-On Reset ....... 10
2.1.6 DDR2 Memory Controller and EMIFA: PRIO_RAISE Bits Should Be Changed From Default
Following Reset ............................................................................................ 10
2.1.7 Device: Heatsink Can Be Used to Lower Case Temperature and Power Consumption ......... 11
2.1.8 McBSP: Receiver and/or Transmitter Must Out of Reset to Enable Frame-Sync Detection ..... 11
2.1.9 McBSP: Performance Degradation Can Be Seen When Using PCI or UTOPIA .................. 11
2.1.10 Boundary Scan: Warnings Relating to the RSV32 and RSV34 Pins May Be Observed When
Using Boundary Scan ..................................................................................... 11
2.1.11 PCI: DSP PCI Cannot Burst More Than 64 Bytes When Used in Master Mode .................. 12
2.1.12 DDR2 Memory Controller: Maximum Addressable Memory Increased to 512MB in 32-bit Mode
................................................................................................................ 12
2.1.13 EMAC: Gigabit Mode Cannot Be Used With CPU Running at Speeds Lower Than 750 MHz .. 12
2.1.14 DDR2 EMIF: Delay Before CKE Goes High With Different Combinations of REFRESH_RATE and
DDR Clock .................................................................................................. 12
2.1.15 Manual Cache Coherence Operation .................................................................... 13
2.1.16 AEA3 Must be Tied High with a 1-kΩ Resisitor if Power is Applied to the SRIO Supply Pins ... 13
2.2 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications .................................. 14
3 Silicon Revision 2.1 Usage Notes and Known Design Exceptions to Functional
Specifications ................................................................................................................... 61
3.1 Usage Notes for Silicon Revision 2.1 ............................................................................... 61
3.2 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications .................................. 62
4 Silicon Revision 2.0 Usage Notes and Known Design Exceptions to Functional
Specifications ................................................................................................................... 73
5 Silicon Revision 1.1 Usage Notes and Known Design Exceptions to Functional
Specifications ................................................................................................................... 74
5.1 Usage Notes for Silicon Revision 1.1 ............................................................................... 74
5.1.1 EMAC: RMII Reference Clock Will Be Changed to Input on Silicon Revision 2.0 and Later .... 74
5.2 Silicon Revision 1.1 Known Design Exceptions to Functional Specifications .................................. 75
Revision History ......................................................................................................................... 81
3
SPRZ234R–December 2005–Revised January 2012 Table of Contents
Submit Documentation Feedback
Copyright © 2005–2012, Texas Instruments Incorporated
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
