Datasheet 搜索 > DSP数字信号处理器 > TI（德州仪器） > TMS320C6455BCTZ8 数据手册 > TMS320C6455BCTZ8 其他数据使用手册 4/82 页
￥ 1410.798
TMS320C6455BCTZ8 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
BFBGA-697
描述:
定点数字信号处理器 697-FCBGA 0 to 90
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P9
技术参数、封装参数在P8P9P10P11P12P13P15P16P17P18P19P20
应用领域在P35P82
导航目录
TMS320C6455BCTZ8数据手册
Page:
of 82 Go
若手册格式错乱，请下载阅览PDF原文件
www.ti.com
List of Figures
1 Lot Trace Code Examples for TMS320C6455 (CTZ/GTZ/ZTZ Packages).......................................... 6
2 Read and Write Synchronous FIFO Interface With Glue Block Diagram............................................ 9
3 Bad TCK Transition ....................................................................................................... 21
4 Good TCK Transition ..................................................................................................... 22
5 Internal Reset Asserted By Reset Controller .......................................................................... 27
6 Example With RESET and PRST Pins Tied High..................................................................... 28
7 Example With PRST and RESET Pins Tied Together ............................................................... 28
8 Example With Independent Power-On Reset, Warm Reset, and PCI Reset Sources ........................... 28
9 Daisy-Chain Example..................................................................................................... 37
10 AECLKOUT at the DSP .................................................................................................. 41
11 66-MHz Buffer Slew and Timing Performance vs Specification Performance..................................... 46
12 L1D Cache Address Mapping............................................................................................ 54
13 Sequence of Events....................................................................................................... 55
14 ISR Workaround Flowchart .............................................................................................. 60
15 IDMA, SDMA, and MDMA Paths........................................................................................ 64
16 QUETCMAP Register (02A0 0280h).................................................................................... 80
List of Tables
1 Lot Trace Codes ............................................................................................................ 6
2 Speed and Temperature Grade Symbolization ......................................................................... 7
3 Silicon Revision Variables ................................................................................................. 7
4 200-μs Delay Calculated Values ........................................................................................ 13
5 7.8125-μs Interval Calculated Values................................................................................... 13
6 Silicon Revision 3.1 Advisory List ....................................................................................... 14
7 Receive Internal Bus Utilization ......................................................................................... 32
8 1 Port 4x mode Using 4 LSUs, NWRITE packets, 3.125 Gbaud.................................................... 32
9 1 Port 1x mode Using 1 LSU, NWRITE packets, 3.125 Gbaud..................................................... 33
10 PCI Slew Rate ............................................................................................................. 46
11 Valid Signal Delay......................................................................................................... 46
12 66-MHz PCI System Timing ............................................................................................. 47
13 C6455/54 Default Master Priorities...................................................................................... 48
14 Value of X for L1D Cache ................................................................................................ 54
15 Silicon Revision 2.1 Advisory List ....................................................................................... 62
16 Stall Conditions on Silicon Revisions ................................................................................... 70
17 Silicon Revision 1.1 Advisory List ....................................................................................... 75
18 TC Connection Matrix..................................................................................................... 79
19 QUETCMAP Register Field Descriptions............................................................................... 80
4
List of Figures SPRZ234R– December 2005– Revised January 2012
Submit Documentation Feedback
Copyright © 2005–2012, Texas Instruments Incorporated
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
