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TMS320C6748EZCED4 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LFBGA-361
描述:
低功耗 C674x 浮点 DSP- 456MHz、SATA 361-NFBGA -40 to 90
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标记信息在P3
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TMS320C6748EZCED4数据手册
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Silicon Revision 2.3 Usage Notes and Known Design Exceptions to Functional Specifications
www.ti.com
2 Silicon Revision 2.3 Usage Notes and Known Design Exceptions to Functional
Specifications
The advisories may not always be enumerated in sequential order and hence some numbers may not
appear in the document.
2.1 Usage Notes for Silicon Revision 2.3
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
2.1.1 USB0: Generic RNDIS Usage Note
On all silicon revisions, when using Generic RNDIS mode, the user should ensure that the DMA
configuration has completed prior to the host starting a transfer. This condition is sometimes violated when
performing a back-to-back data transfers (not transactions). If a new transfer is scheduled by a host while
the device is working on the previous transfer and the data transfer size for the new transfer is different
than the previous transfer data size, then there exists a contention between the two transfer sizes creating
undesired behavior resulting with a DMA lock up. A case in point where this violation could happen is
demonstrated by the example below.
A user configures the DMA in Generic RNDIS mode expecting a data size of 512 bytes or less from a
host. The host sends 512 bytes or less of data to the device. While the device is in the process of working
on the received data to figure out the size of the next data transfer, the host starts a new data transfer
addressing the same endpoint. Since the endpoint FIFO is empty, the device accepts the data and the
DMA starts to transfer the received data from the receive FIFO to memory. At the same time, the
application on the device side finishes and figures out the next transfer data size (using the data received
from previous transfer) and reconfigures the Generic DMA Size register for the second transfer. If the
second transfer size is different from the first transfer size, the contention happens at this point. The host
has already started the second transfer prior to the device re-configuring the DMA parameters. The
application on the device side, updates the DMA size register content for the second transfer while the
DMA is in the middle of the second transfer using the DMA size register content of the first transfer. This
effectively results with altering the DMA size register content while the DMA is in the middle of a transfer.
Changing DMA parameters while in the middle of a transfer is not allowed and when done it will create
undesirable outcomes.
Workaround: This is not a bug and for this reason, there exists no workaround. This is a caution for the
user to be aware of this issue and hence to ensure that this scenario is avoided. If there exists an idle time
in between the two back-to-back transfers, this issue will not exist. When expecting a back-to-back
transfer where RNDIS mode can not be used, the user needs to use TRANSPARENT mode. When using
TRANSPARENT mode, the application will be receiving more interrupts, that is, interrupt will be generated
on each USB packets as opposed to receiving a single interrupt on the completion of a transfer.
2.1.2 USB0: Isochronous Interrupt Loading Usage Note
On all silicon revisions, when the USB Controller Endpoint is enabled to handle Isochronous type of
transfer, the controller supports a single configuration for interrupt generation, which is for interrupt to be
generated for every ISO packet received or sent, that is, transfer size is equal to packet size. The option
of generating interrupt on multiple ISO packets received or sent is not available. Since ISO transfer can be
scheduled to happen on every micro-frame or frame, the number of interrupts generated could overwhelm
the system. This is not a problem as long as there is enough CPU power available to handle all interrupts.
However, some applications may be running low on available CPU time and may desire to
service/process multiple ISO packets at a time. The option for handling ISO interrupts in a batch is not
available. The user should ensure that enough CPU power is available to handle all ISO interrupts in order
to avoid missing interrupts resulting with missing ISO packets.
4
TMS320C6748 Fixed- and Floating-Point DSP Silicon Revisions 2.3, 2.1, 2.0, SPRZ303H–June 2009–Revised March 2014
1.1 and 1.0
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