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P1013NXN2HFB 产品设计参考手册 - NXP（恩智浦）
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NXP（恩智浦）
分类:
微处理器
封装:
BGA-689
描述:
PowerPC系列 1.055GHz
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P1013NXN2HFB数据手册
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若手册格式错乱，请下载阅览PDF原文件
e500 Software Optimization Guide (eSOG), Rev. 0
2 Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Overview
identifies which e500 functionality is defined by the EIS.
Both documents are available at www.freescale.com. The CWG is available on the IBM website,
www.ibm.com.
1.1 Terminology and Conventions
This section provides an alphabetical glossary of terms used in this document. These definitions offer a
review of commonly used terms and point out specific ways these terms are used.
NOTE
Some of these definitions differ slightly from those used to describe
previous processors that implement the PowerPC architecture, in particular
with respect to dispatch, issue, finishing, retirement, and write back, so
please read this glossary carefully.
• Branch prediction—The process of guessing the direction and target of a branch. Branch direction
prediction involves guessing whether a branch is taken. Target prediction involves guessing the
target address of a branch. The e500 core does not use the Book E–defined hint bits in the BO
operand for static prediction. Clearing BUCSR[BPEN] disables dynamic branch prediction, in
which case the e500 predicts every branch as not taken.
• Branch resolution—The determination in the branch execution unit of whether a branch prediction
is correct. If it is, instructions following the predicted branch that may have been speculatively
executed can complete (see Complete). If it is incorrect, the processor redirects fetching to the
proper path and squashes instructions on the mispredicted path (and any of their results) when the
mispredicted branch completes.
• Complete—An instruction is eligible to complete after it finishes executing and makes its results
available for the next instruction. Instructions must complete in order from the bottom two entries
of the completion queue (CQ). To ensure the appearance of serial execution, the completion unit
coordinates how instructions (which may have executed out of order) affect architected registers.
This guarantees that the completed instruction and all previous instructions can cause no
exceptions. An instruction completes when it is retired, that is, deleted from CQ.
• Decode—The decode stage determines the issue queue to which each instruction is dispatched (see
Dispatch) and determines whether the required space is available in both that issue queue and the
completion queue. If space is available, it decodes instructions supplied by the instruction queue,
renames any source/target operands, and dispatches them to the appropriate issue queues.
• Dispatch—Dispatch is the event at the end of the decode stage during which instructions are passed
to the issue queues and tracking of program order is passed to the completion queue.
• Fetch—The process of bringing instructions from memory (such as a cache or system memory)
into the instruction queue.
• Finish—An executed instruction finishes by signaling the completion queue that execution has
concluded. An instruction is said to be finished (but not complete) when the execution results have
been saved in rename registers and made available to subsequent instructions, but the completion
unit has not yet updated the architected registers.
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