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TMS320C5535AZHHA05 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
BGA-144
描述:
TMS320C5535 ， C5534 ， C5533 ， C5532定点数字信号处理器 TMS320C5535, C5534, C5533,C5532 FIXED-POINT DIGITAL SIGNAL PROCESSORS
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P344P455Hot
典型应用电路图在P285P286
原理图在P37P38P118P138P163P190P204P205P255P256P285P310
功能描述在P52P127P137
应用领域在P558
导航目录
TMS320C5535AZHHA05数据手册
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5
SPRUH87H–August 2011–Revised April 2016
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Copyright © 2011–2016, Texas Instruments Incorporated
Contents
6.1 Introduction ................................................................................................................ 204
6.1.1 Purpose of the Peripheral....................................................................................... 204
6.1.2 Features........................................................................................................... 204
6.1.3 Functional Block Diagram ...................................................................................... 204
6.1.4 Supported Use Case Statement............................................................................... 204
6.1.5 Industry Standard(s) Compliance Statement................................................................. 205
6.2 Peripheral Architecture................................................................................................... 205
6.2.1 Clock Control..................................................................................................... 207
6.2.2 Signal Descriptions .............................................................................................. 207
6.2.3 Pin Multiplexing .................................................................................................. 208
6.2.4 Protocol Descriptions............................................................................................ 208
6.2.5 Data Flow in the Input/Output FIFO........................................................................... 209
6.2.6 Data Flow in the Data Registers (SDDRR and SDDXR) ................................................... 211
6.2.7 FIFO Operation During Card Read Operation ............................................................... 212
6.2.8 FIFO Operation During Card Write Operation ............................................................... 213
6.2.9 Reset Considerations ........................................................................................... 215
6.2.10 Programming and Using the SD Controller ................................................................. 216
6.2.11 Interrupt Support................................................................................................ 220
6.2.12 DMA Event Support ............................................................................................ 220
6.2.13 Emulation Considerations ..................................................................................... 220
6.3 Procedures for Common Operations................................................................................... 221
6.3.1 Card Identification Operation................................................................................... 221
6.3.2 eMMC/SD Mode Single-Block Write Operation Using CPU................................................ 222
6.3.3 eMMC/SD Mode Single-Block Write Operation Using DMA ............................................... 223
6.3.4 eMMC/SD Mode Single-Block Read Operation Using CPU ............................................... 224
6.3.5 eMMC/SD Mode Single-Block Read Operation Using DMA............................................... 225
6.3.6 eMMC/SD Mode Multiple-Block Write Operation Using CPU.............................................. 226
6.3.7 eMMC/SD Mode Multiple-Block Write Operation Using DMA ............................................. 227
6.3.8 eMMC/SD Mode Multiple-Block Read Operation Using CPU.............................................. 228
6.3.9 eMMC/SD Mode Multiple-Block Read Operation Using DMA ............................................. 229
6.3.10 SD High Speed Mode.......................................................................................... 230
6.3.11 SDIO Card Function............................................................................................ 230
6.4 Registers................................................................................................................... 231
6.4.1 SD Control Register (SDCTL).................................................................................. 233
6.4.2 SD Memory Clock Control Register (SDCLK) ............................................................... 234
6.4.3 SD Status Register 0 (SDST0)................................................................................. 235
6.4.4 SD Status Register 1 (SDST1)................................................................................. 237
6.4.5 SD Interrupt Mask Register (SDIM) ........................................................................... 238
6.4.6 SD Response Time-Out Register (SDTOR).................................................................. 239
6.4.7 SD Data Read Time-Out Register (SDTOD)................................................................. 240
6.4.8 SD Block Length Register (SDBLEN)......................................................................... 240
6.4.9 SD Number of Blocks Register (SDNBLK)................................................................... 241
6.4.10 SD Number of Blocks Counter Register (SDNBLC) ....................................................... 241
6.4.11 SD Data Receive Register (SDDRR1) and (SDDRR2).................................................... 242
6.4.12 SD Data Transmit Registers (SDDXR1) and (SDDXR2).................................................. 243
6.4.13 eMMC Command Registers (MMCSD1) and (MMCSD2)................................................. 244
6.4.14 SD Argument Registers (SDARG1) and (SDARG2)....................................................... 246
6.4.15 SD Response Registers (SDRSP0-SDRSP7) .............................................................. 247
6.4.16 SD Data Response Register (SDDRSP) .................................................................... 249
6.4.17 SD Command Index Register (SDCIDX) .................................................................... 249
6.4.18 SDIO Control Register (SDIOCTL)........................................................................... 250
6.4.19 SDIO Status Register 0 (SDIOST0).......................................................................... 250
6.4.20 SDIO Interrupt Enable Register (SDIOIEN)................................................................. 251
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