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TMS320C6745DPTPD4 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LQFP-176
描述:
DSP)，Texas Instruments德州仪器数字信号处理器是微处理器，带有一个优化的体系结构，用于数字信号处理的运算需求。### 数字信号处理器，Texas Instruments
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TMS320C6745DPTPD4数据手册
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Contents
Preface ...................................................................................................................................... 15
1 Overview .......................................................................................................................... 17
1.1 Introduction ................................................................................................................. 18
1.2 C674x Megamodule Overview ........................................................................................... 19
1.2.1 C674x CPU ........................................................................................................ 19
1.2.2 Level 1 Program (L1P) Memory Controller .................................................................... 19
1.2.3 Level 1 Data (L1D) Memory Controller ........................................................................ 19
1.2.4 Level 2 (L2) Memory Controller ................................................................................. 19
1.2.5 Internal DMA (IDMA) ............................................................................................. 20
1.2.6 Bandwidth Management (BWM) ................................................................................ 20
1.2.7 Interrupt Controller (INTC) ....................................................................................... 20
1.2.8 Memory Protection Architecture (MPA) ........................................................................ 21
1.2.9 Power-Down Controller (PDC) .................................................................................. 21
1.2.10 Extended Memory Controller (EMC) .......................................................................... 21
2 Level 1 Program Memory and Cache .................................................................................... 23
2.1 Introduction ................................................................................................................. 24
2.1.1 Purpose of the Level 1 Program (L1P) Memory and Cache ................................................ 24
2.1.2 Features ........................................................................................................... 24
2.2 Terms and Definitions ..................................................................................................... 24
2.3 L1 Program Memory Architecture ....................................................................................... 24
2.3.1 L1P Memory ....................................................................................................... 24
2.4 L1P Cache .................................................................................................................. 25
2.4.1 L1P Cache Architecture ......................................................................................... 25
2.4.2 Replacement and Allocation Strategy ......................................................................... 26
2.4.3 L1P Mode Change Operations ................................................................................. 26
2.4.4 L1P Freeze Mode ................................................................................................ 27
2.5 Program Initiated Coherence Operations .............................................................................. 29
2.5.1 Global Coherence Operation .................................................................................... 29
2.5.2 Block Coherence Operation ..................................................................................... 29
2.6 L1P Cache Control Registers ............................................................................................ 30
2.6.1 Memory Mapped Cache Control Register Overview ......................................................... 30
2.6.2 CPU Cache Control Registers .................................................................................. 30
2.6.3 L1P Cache Configuration Registers ............................................................................ 31
2.6.4 Privilege and Cache Control Operations ...................................................................... 34
2.7 L1P Performance .......................................................................................................... 34
2.7.1 L1P Miss Penalty ................................................................................................. 34
2.7.2 L1P Miss Pipelining .............................................................................................. 34
2.8 Power-Down Support ..................................................................................................... 36
2.8.1 Static Power-Down ............................................................................................... 36
2.8.2 Dynamic Power-Down ........................................................................................... 36
2.8.3 Feature-Oriented Power-Down ................................................................................. 36
2.9 L1P Memory Protection ................................................................................................... 37
2.9.1 Protection Checks on L1P Accesses .......................................................................... 37
2.9.2 Memory Protection Registers ................................................................................... 38
3 Level 1 Data Memory and Cache ......................................................................................... 49
3
SPRUFK5A–August 2010 Contents
Copyright © 2010, Texas Instruments Incorporated
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