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TMS320C6745DPTPD4 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LQFP-176
描述:
DSP)，Texas Instruments德州仪器数字信号处理器是微处理器，带有一个优化的体系结构，用于数字信号处理的运算需求。### 数字信号处理器，Texas Instruments
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TMS320C6745DPTPD4数据手册
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4.5.1 L2 Memory Dynamic Power-Down ........................................................................... 107
4.5.2 L2 Memory Static Power-Down ............................................................................... 108
4.5.3 L2 Power-Down Control Registers ............................................................................ 109
4.6 L2 Memory Protection ................................................................................................... 112
4.6.1 Protection Checks on CPU, IDMA and Other System Master Accesses ................................ 112
4.6.2 L2 Memory Protection Registers .............................................................................. 113
4.6.3 Protection Checks on Accesses to Memory Protection Registers ........................................ 124
5 Internal Direct Memory Access (IDMA) Controller ................................................................ 125
5.1 Introduction ............................................................................................................... 126
5.1.1 Purpose of the Internal Direct Memory Access (IDMA) Controller ....................................... 126
5.1.2 Features .......................................................................................................... 126
5.2 Terms and Definitions ................................................................................................... 126
5.3 IDMA Architecture ........................................................................................................ 127
5.3.1 IDMA Channel 0 ................................................................................................. 127
5.3.2 IDMA Channel 1 ................................................................................................. 129
5.4 Registers .................................................................................................................. 131
5.4.1 IDMA Channel 0 Status Register (IDMA0_STAT) .......................................................... 132
5.4.2 IDMA Channel 0 Mask Register (IDMA0_MASK) .......................................................... 133
5.4.3 IDMA Channel 0 Source Address Register (IDMA0_SOURCE) .......................................... 134
5.4.4 IDMA Channel 0 Destination Address Register (IDMA0_DEST) ......................................... 135
5.4.5 IDMA Channel 0 Count Register (IDMA0_COUNT) ........................................................ 136
5.4.6 IDMA Channel 1 Status Register (IDMA1_STAT) .......................................................... 137
5.4.7 IDMA Channel 1 Source Address Register (IDMA1_SOURCE) .......................................... 138
5.4.8 IDMA Channel 1 Destination Address Register (IDMA1_DEST) ......................................... 139
5.4.9 IDMA Channel 1 Count Register (IDMA1_COUNT) ........................................................ 140
5.5 Privilege Levels and IDMA Operation ................................................................................. 141
6 Bandwidth Management Architecture ................................................................................. 143
6.1 Introduction ............................................................................................................... 144
6.1.1 Purpose of the Bandwidth Management ..................................................................... 144
6.1.2 Resource Bandwidth Protected by Bandwidth Management .............................................. 144
6.1.3 Requestors Managed by Bandwidth Management ......................................................... 144
6.1.4 Terms and Definitions .......................................................................................... 144
6.2 Architecture ............................................................................................................... 145
6.2.1 Bandwidth Arbitration via Priority Levels ..................................................................... 145
6.2.2 Priority Level: -1 ................................................................................................. 145
6.2.3 Priority Declaration .............................................................................................. 145
6.3 Registers .................................................................................................................. 146
6.3.1 CPU Arbitration Control Register (CPUARBD, CPUARBU, CPUARBE) ................................ 147
6.3.2 User Coherence Arbitration Control Register (UCARBD, UCARBU) .................................... 149
6.3.3 IDMA Arbitration Control Register (IDMAARBD, IDMAARBU, IDMAARBE) ............................ 150
6.3.4 Slave DMA Arbitration Control Register (SDMAARBD, SDMAARBU, SDMAARBE) .................. 151
6.3.5 Master DMA Arbitration Control Register (MDMAARBE) .................................................. 152
6.4 Privilege and Bandwidth Management Registers .................................................................... 153
7 Interrupt Controller .......................................................................................................... 155
7.1 Introduction ............................................................................................................... 156
7.1.1 Purpose of the C674x Megamodule Interrupt Controller (INTC) .......................................... 156
7.1.2 Features .......................................................................................................... 156
7.1.3 Functional Block Diagram ...................................................................................... 157
7.1.4 Terms and Definitions .......................................................................................... 157
7.2 Interrupt Controller Architecture ........................................................................................ 158
7.2.1 Event Registers ................................................................................................. 158
7.2.2 Event Combiner ................................................................................................. 160
7.2.3 Interrupt Selector ................................................................................................ 162
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SPRUFK5A–August 2010 Contents
Copyright © 2010, Texas Instruments Incorporated
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