Datasheet 搜索 > DSP数字信号处理器 > TI（德州仪器） > TMS320DM6446BZWT 数据手册 > TMS320DM6446BZWT 产品设计参考手册 1/227 页
器件3D模型￥ 137.601
TMS320DM6446BZWT 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LFBGA-361
描述:
达芬奇数字媒体片上系统 361-NFBGA 0 to 85
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P23P71Hot
原理图在P5P84P91P93P94
封装尺寸在P224
标记信息在P224P225
封装信息在P223P224P225
技术参数、封装参数在P14P85P88P89P90P91P92P93P94P95P96P97
应用领域在P2P227
电气规格在P14P87P88P89P90P91P92P93P94P95P96P97
导航目录
TMS320DM6446BZWT数据手册
Page:
of 227 Go
若手册格式错乱，请下载阅览PDF原文件
TMS320DM6446
www.ti.com
SPRS283H–DECEMBER 2005–REVISED SEPTEMBER 2010
TMS320DM6446
Digital Media System-on-Chip
Check for Samples: TMS320DM6446
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
12
• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture
– 513-, 594-, 810-MHz C64x+™ Clock Rates – 32K-Byte L1P Program RAM/Cache (Direct
Mapped)
– 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock
Rates – 80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
– Eight 32-Bit C64x+ Instructions/Cycle
– 64K-Byte L2 Unified Mapped RAM/Cache
– 4104, 4752, 6480 C64x+ MIPS
(Flexible RAM/Cache Allocation)
– Fully Software-Compatible With C64x /
• ARM926EJ-S Core
ARM9™
– Support for 32-Bit and 16-Bit (Thumb®
– Extended Temperature Devices Available
Mode) Instruction Sets
• Advanced Very-Long-Instruction-Word (VLIW)
– DSP Instruction Extensions and Single Cycle
TMS320C64x+™ DSP Core
MAC
– Eight Highly Independent Functional Units
– ARM® Jazelle® Technology
• Six ALUs (32-/40-Bit), Each Supports
– EmbeddedICE-RT™ Logic for Real-Time
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Debug
Arithmetic per Clock Cycle
• ARM9 Memory Architecture
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock – 16K-Byte Instruction Cache
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
– 8K-Byte Data Cache
Results) per Clock Cycle
– 16K-Byte RAM
– Load-Store Architecture With Non-Aligned
– 8K-Byte ROM
Support
• Embedded Trace Buffer™ (ETB11™) With 4KB
– 64 32-Bit General-Purpose Registers
Memory for ARM9 Debug
– Instruction Packing Reduces Code Size
• Endianness: Little Endian for ARM and DSP
– All Instructions Conditional
• Video Imaging Co-Processor (VICP)
– Additional C64x+™ Enhancements
• Video Processing Subsystem
• Protected Mode Operation
– Front End Provides:
• Exceptions Support for Error Detection
• CCD and CMOS Imager Interface
and Program Redirection
• BT.601/BT.656 Digital YCbCr 4:2:2
• Hardware Support for Modulo Loop
(8-/16-Bit) Interface
Operation
• Preview Engine for Real-Time Image
• C64x+ Instruction Set Features
Processing
– Byte-Addressable (8-/16-/32-/64-Bit Data)
• Glueless Interface to Common Video
– 8-Bit Overflow Protection
Decoders
– Bit-Field Extract, Set, Clear
• Histogram Module
– Normalization, Saturation, Bit-Counting
• Auto-Exposure, Auto-White Balance and
– Compact 16-Bit Instructions Auto-Focus Module
– Additional Instructions to Support Complex • Resize Engine
Multiplies
– Resize Images From 1/4x to 4x
– Separate Horizontal/Vertical Control
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
