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TMS320DM6446BZWT 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LFBGA-361
描述:
达芬奇数字媒体片上系统 361-NFBGA 0 to 85
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P23P71Hot
原理图在P5P84P91P93P94
封装尺寸在P224
标记信息在P224P225
封装信息在P223P224P225
技术参数、封装参数在P14P85P88P89P90P91P92P93P94P95P96P97
应用领域在P2P227
电气规格在P14P87P88P89P90P91P92P93P94P95P96P97
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TMS320DM6446BZWT数据手册
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TMS320DM6446
www.ti.com
SPRS283H–DECEMBER 2005–REVISED SEPTEMBER 2010
1.2 Description
The TMS320DM6446 (also referenced as DM6446) leverages TI’s DaVinci™ technology to meet the
networked media encode and decode application processing needs of next-generation embedded devices.
The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, high processing performance, and long battery life through the
maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core incorporates:
• A coprocessor 15 (CP15) and protection module
• Data and program Memory Management Units (MMUs) with table look-aside buffers.
• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the
TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation
high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas
Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a
code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of
the C64x+™ DSP with added functionality and an expanded instruction set.
Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™
DSP and C64x+™ CPU, respectively.
With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details
on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level
cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the
Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a
Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio
serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers;
1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware
handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory
interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a
higher speed synchronous memory interface for DDR2.
Copyright © 2005–2010, Texas Instruments Incorporated Digital Media System-on-Chip (DMSoC) 3
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