Datasheet 搜索 > DSP数字信号处理器 > TI（德州仪器） > TMS320DM6446BZWT 数据手册 > TMS320DM6446BZWT 产品设计参考手册 2/227 页
器件3D模型￥ 137.038
TMS320DM6446BZWT 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LFBGA-361
描述:
达芬奇数字媒体片上系统 361-NFBGA 0 to 85
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P23P71Hot
原理图在P5P84P91P93P94
封装尺寸在P224
标记信息在P224P225
封装信息在P223P224P225
技术参数、封装参数在P14P85P88P89P90P91P92P93P94P95P96P97
应用领域在P2P227
电气规格在P14P87P88P89P90P91P92P93P94P95P96P97
导航目录
TMS320DM6446BZWT数据手册
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若手册格式错乱，请下载阅览PDF原文件
TMS320DM6446
SPRS283H–DECEMBER 2005–REVISED SEPTEMBER 2010
www.ti.com
• Video Processing Subsystem (Continued) • One Serial Peripheral Interface (SPI) With Two
Chip-Selects
– Back End Provides:
• Master/Slave Inter-Integrated Circuit (I
2
C Bus™)
• Hardware On-Screen Display (OSD)
• Audio Serial Port (ASP)
• Four 54-MHz DACs for a Combination of
– I2S
– Composite NTSC/PAL Video
– AC97 Audio Codec Interface
– Luma/Chroma Separate
Video (S-video) – Standard Voice Codec Interface (AIC12)
– Component (YPbPr or RGB) Video • 10/100 Mb/s Ethernet MAC (EMAC)
(Progressive)
– IEEE 802.3 Compliant
• Digital Output
– Media Independent Interface (MII)
– 8-/16-bit YUV or up to 24-Bit RGB
• VLYNQ™ Interface (FPGA Interface)
– HD Resolution
• Host Port Interface (HPI) with 16-Bit
– Up to 2 Video Windows Multiplexed Address/Data
• External Memory Interfaces (EMIFs) • USB Port With Integrated 2.0 PHY
– 32-Bit DDR2 SDRAM Memory Controller With – USB 2.0 High-/Full-Speed (480-Mbps) Client
256M-Byte Address Space (1.8-V I/O)
– USB 2.0 High-/Full-/Low-Speed Host
• Up to 167-MHz Controller (A-513, -594) (Mini-Host, Supporting One External
Device)
• Up to 189-MHz Controller (-810)
• Three Pulse Width Modulator (PWM) Outputs
– Asynchronous16-Bit-Wide EMIF (EMIFA)
With 128M-Byte Address Reach • On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash or UART
• Flash Memory Interfaces
• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
– NOR (8-/16-Bit-Wide Data)
• Individual Power-Saving Modes for ARM/DSP
– NAND (8-/16-Bit-Wide Data)
• Flexible PLL Clock Generators
• Flash Card Interfaces
• IEEE-1149.1 (JTAG) Boundary-
– Multimedia Card (MMC)/Secure Digital (SD)
Scan-Compatible
with Secure Data I/O (SDIO)
• Up to 71 General-Purpose I/O (GPIO) Pins
– Compact Flash Controller With True IDE
(Multiplexed With Other Device Functions)
Mode
• 361-Pin Pb-Free BGA Package
– SmartMedia
(ZWT Suffix), 0.8-mm Ball Pitch
• Enhanced Direct-Memory-Access (EDMA3)
• 0.09-mm/6-Level Cu Metal Process (CMOS)
Controller (64 Independent Channels)
• 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers) • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V
Internal (810 only)
• One 64-Bit Watch Dog Timer
• Applications:
• Three UARTs (One with RTS and CTS Flow
Control) – Digital Media
– Networked Media Encode/Decode
– Video Imaging
2 Digital Media System-on-Chip (DMSoC) Copyright © 2005–2010, Texas Instruments Incorporated
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