Datasheet 搜索 > 开发套件 > TI（德州仪器） > CDCEL949PERF-EVM 数据手册 > CDCEL949PERF-EVM 用户编程技术手册 6/41 页
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CDCEL949PERF-EVM 用户编程技术手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
开发套件
描述:
TEXAS INSTRUMENTS CDCEL949PERF-EVM 评估模块, 时钟发生器, CDCEL949
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P4P5Hot
典型应用电路图在P1P27P28P29P30P31
原理图在P1P13
封装尺寸在P35P37P38
标记信息在P35P36
封装信息在P34P35P36P37P38
技术参数、封装参数在P5
应用领域在P1P41
电气规格在P7P8
导航目录
CDCEL949PERF-EVM数据手册
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6
CDCE949
,
CDCEL949
SCAS844F –AUGUST 2007–REVISED OCTOBER 2016
www.ti.com
Product Folder Links: CDCE949 CDCEL949
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
(1) For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family
(SCAA085).
(2) Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
V
DD
Device supply voltage 1.7 1.8 1.9 V
V
DD(OUT)
Output Yx supply voltage
CDCE949 2.3 3.6
V
CDCEL949 1.7 1.9
V
IL
Low level input voltage LVCMOS 0.3 × V
DD
V
V
IH
High level input voltage LVCMOS 0.7 × V
DD
V
V
I(thresh)
Input voltage threshold LVCMOS 0.5 × V
DD
V
V
IS
Input voltage
S0 0 1.9
V
S1, S2, SDA, SCL,
V
Ithresh
= 0.5 × V
DD
0 3.6
V
ICLK
Input voltage CLK 0 1.9 V
I
OH
/I
OL
Output current
V
DDout
= 3.3 V ±12 mA
V
DDout
= 2.5 V ±10 mA
V
DDout
= 1.8 V ±8 mA
C
L
Output load LVCMOS 10 pF
T
A
Operating free-air temperature –40 85 °C
CRYSTAL AND VCXO
(1)
f
Xtal
Crystal Input frequency (fundamental mode) 8 27 32 MHz
ESR Effective series resistance 100 Ω
f
PR
Pulling (0 V ≤ V
Ctrl
≤ 1.8 V)
(2)
±120 ±150 ppm
V
(Ctrl)
Frequency control voltage 0 V
DD
V
C
0
/C
1
Pullability ratio 220
C
L
On-chip load capacitance at Xin and Xout 0 20 pF
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
7.4 Thermal Information
THERMAL METRIC
(1)
CDCEx949
UNITPW (TSSOP)
24 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
Airflow 0 (LFM) 91
°C/W
Airflow 150 (LFM) 75
Airflow 200 (LFM) 74
Airflow 250 (LFM) 73
Airflow 500 (LFM) 65
θ
JCtop
Junction-to-case (top) thermal resistance 0.5 °C/W
θ
JB
Junction-to-board thermal resistance 52 °C/W
ψ
JT
Junction-to-top characterization parameter 0.5 °C/W
ψ
JB
Junction-to-board characterization parameter 50.1 °C/W
θ
JCbot
Junction-to-case (bottom) thermal resistance 50 °C/W
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