Datasheet 搜索 > 微处理器 > NXP（恩智浦） > P2020NXN2MHC 数据手册 > P2020NXN2MHC 用户编程技术手册 2/35 页
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P2020NXN2MHC 用户编程技术手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
PBGA-689
描述:
微处理器, QorIQ系列QorIQ P系列, 32位, 1.2 GHz, 0.95V至1.05V, BGA-689
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P2020NXN2MHC数据手册
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PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations, Rev. 4
2 Freescale Semiconductor
Configuration guidelines
1 Configuration guidelines
When selecting values for the memory controller registers, use the following steps:
1. Obtain the data sheet for the DDR SDRAM chip (or DIMM) used.
2. Using the values provided in the DDR data sheet, configure the register values per corresponding
parameters. Values can be stated in the following ways in the DDR data sheet:
— As the number of memory clocks, and it can be directly used for configuring the registers
— In units of fractions of a second, and the value must be divided by the memory clock period to
obtain the number of clocks. If the memory frequency clock is lower than the DDR data sheet
rating, the actual memory frequency should be used to calculate the memory clock period. For
example, if a DDR3-1067 data sheet provides a value of 15 ns for a given parameter (for
example, tRP min = 15 ns), and the memory clock operates at 333.5 MHz (or a data rate of
667 Mbps), then the number of clocks is calculated by first finding the operating memory
period (1/333.5 MHz = 3.0 ns) and next dividing the value by period 15 ns/3.0 ns = 5 clk. As
indicated, a higher-rated memory can operate in lower frequencies. The DDR3-1067 is a
common DDR3 memory, but per the JEDEC specification, DDR3-1067 (or any other
JEDEC-compliant DDR3 DRAM) can operate at a data rate down to 600 Mbps.
3. Set the remaining memory register settings as specified in the applicable device reference manual
and per additional information provided in this application note.
Based on the most commonly observed user-error in the memory controller register setting for DDR3,
special attention must be paid to the following items:
• Selecting and validating the following fields:
— DDR_SDRAM_CLK_CNTL[CLK_ADJUST]
— DDR_WRLVL_CNTL[WRLVL_START]
— TIMING_CFG_5[R/WODT_ON, R/WODT_OFF]
• Selecting and verifying CAS latency, write latency, and additive latency
• Confirming that all DDR mode register values match DDR controller configuration registers,
especially the CAS latency, additive latency, burst type and write recovery settings
• Verifying whether the registered or unbuffered DIMMs are used
• Verifying the minimum value of four clock cycles are observed for the tWTR, tRRD, and tRTP
fields
4. Disable the clocks that are not used via the DDRCLKDR register. By default, all clocks are
operational, but not all clock signals are used in a given application. Therefore, by disabling the
unused clocks, it first lowers the power consumption and then lowers the unused switching
activity in the part. DDRCLKDR is not a part of the memory controller register set; it is located in
the global utility register section.
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