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PIC16F628A-I/ML 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
QFN-28
描述:
PIC16F627A/628A/648A 微控制器Microchip 的 PIC16F 系列微控制器 8 位 MCU，将 Microchip 的 PIC® 体系架构融入到引脚和封装选件中，从节省空间的 14 引脚设备到功能丰富的 64 引脚设备。 带有基线、中级或增强型中级体系架构的设备提供多种不同的外围设备组合，可谓设计人员提供灵活性，并为应用提供选择。 PIC16F627A/628A/648A 系列微控制器基于 Microchip 中档内核，带 8 层深硬件堆栈和 35 个指令。 这些 MCU 提供高达 5 MIPS、高达 3.5 K 字节的程序内存，224 字节 RAM 和多达 128 字节的数据 EEPROM。 板载是一个振荡器，工厂校准到 ±1% 精确度。### 微控制器功能最大 20 MHz CPU 速度 35 个指令 8 级硬件堆栈 16 个输入/输出引脚 通电重置 (POR) 通电计时器 (PWRT) 振荡器启动计时器 (OST) 掉电重置 (BOR) 监控计时器 (WDT) 低电压编程 (LVP) 在线串行编程 (ICSP) ### 外设两个比较器 捕获/比较/PWM 模块 两个 8 位计时器 一个 16 位计时器 ### PIC16 微控制器
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PIC16F628A-I/ML数据手册
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PIC16F627A/628A/648A
DS41196G-page 6 Preliminary © 2007 Microchip Technology Inc.
The optional 16-bit data word will either be an input to,
or an output from the PIC
®
microcontroller, depending
on the command. Load Data commands will be input,
and Read Data commands will be output. The 16-bit
data word only contains 14 bits of data to conform to the
14-bit program memory word. The 14 bits are centered
within the 16-bit word, padded with a leading and trail-
ing zero.
Program/Verify mode may be entered via one of two
methods. High voltage Program/Verify is entered by
holding CLOCK and DATA pins low while raising MCLR
first, then VDD as shown in Figure 2-2. Low voltage
Program/Verify mode is entered by raising V
DD, then
MCLR
and PGM, as shown in Figure 2-3. The PC will
be set to ‘0’ upon entering into Program/Verify mode.
The PC can be changed by the execution of either an
increment PC command, or a Load Configuration
command, which sets the PC to 0x2000.
All other logic is held in the Reset state while in
Program/Verify mode. This means that all I/O are in the
Reset state (high-impedance inputs).
If LVP is not being used for programming and the LVP
Configuration bit is set (i.e., LVP feature is enabled),
the PGM pin must not be allowed to toggle while
programming. The PGM pin is edge sensitive and if an
edge is detected during programming, it may cause the
PC to reset. If the LVP feature is disabled, the PGM pin
will have no effect on programming.
FIGURE 2-2: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
FIGURE 2-3: ENTERING LOW
VOLTAGE PROGRAM/
VERIFY MODE
Note: The LVP feature is enabled by default
when the LVP bit of the Configuration
Word is set.
MCLR
VDD
DATA
CLOCK
Tppdp Thld0
LVP
Note: If the LVP fuse is enabled, PGM should be
held low to prevent inadvertent entry into LVP
mode.
VDD
PGM
DATA
CLOCK
Tppdp
MCLR
TlvppThld0
Note: If the device is in LVP mode, raising V
PP to
V
IHH will override LVP mode.
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