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DSPIC33FJ128GP802-E/MM 其他数据使用手册 - Microchip（微芯）
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Microchip（微芯）
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微控制器
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QFN-28
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DSPIC33FJ128GP802-E/MM 管装
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DSPIC33FJ128GP802-E/MM数据手册
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© 2009 Microchip Technology Inc. DS01249A-page 1
AN1249
INTRODUCTION
This application note is focused on helping customers
understand the role of Direct Memory Access (DMA) in
implementing the functionality of the Enhanced
Controller Area Network (ECAN™) module.
This material will be of interest to engineers who use
the CAN protocol for communication.
The information presented assumes you have a
working knowledge of the CAN protocol. For those who
are new to CAN, refer to the following resources
available from Microchip:
• CAN resources such as application notes and
Web seminars can be accessed at:
www.microchip.com/CAN
• Sample code for various dsPIC
®
DSC devices
can be accessed at:
www.microchip.com/codeexamples
• Our Regional Training Centers (RTC) can help
you get started with ECAN and offer a range of
classes. For more information, visit:
www.microchip.com/rtc
• Additional material at the end of this application
note includes references to literature and
vocabulary
OVERVIEW
The ECAN module works in conjunction with the DMA
controller in dsPIC33F and PIC24H devices. The DMA
controller is a very important subsystem in Microchip’s
high-performance 16-bit dsPIC33F and PIC24H
devices. The DMA controller allows data transfer from
RAM to a peripheral and vice versa without any CPU
assistance, and operates across its own data bus and
address bus with no impact on CPU operation.
The DMA subsystem supports eight independent
channels. Because each channel is unidirectional, two
channels must be allocated to read and write to the
ECAN peripheral using DMA. One channel is allocated
for reading messages from the ECAN peripheral and
the other channel is allocated for writing messages to
the ECAN peripheral.
When more than one DMA channel receives a
request to transfer data, a simple fixed-priority
scheme that is based on the channel number dictates
the specific channel that completes the transfer and
the channels that are left pending. Each channel has
a fixed priority. The channels with a lower number
have higher priority, with channel 0 having the highest
priority, and channel 7 having the lowest priority.
Each dsPIC33F or PIC24H device contains up to
2 Kbytes of Dual Port SRAM (DPSRAM), which is
adequate to concurrently support multiple buffers for
several peripherals. Figure 1 highlights the DMA
integration with the architecture of dsPIC33F and
PIC24H devices. The CPU communicates with
conventional SRAM across the data space X-bus
known as the CPU X-bus, as shown in Figure 1. It also
communicates to port 1 of the new dual port SRAM
block across the same X-bus.
The CPU communicates to the ECAN peripheral
across a separate peripheral data space bus known as
the CPU Peripheral X-bus, shown in Figure 1, which
also resides in the X data space. The DMA controller
communicates with port 2 of the dual port SRAM and
the DMA port of ECAN module across a dedicated
DMA transfer bus known as the DMA X-bus.
Author: Jatinder Gharoo
Microchip Technology Inc.
ECAN™ Operation with DMA on dsPIC33F and PIC24H Devices
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