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MPC8308CVMAGDA 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-473
描述:
NXP MPC8308CVMAGDA 芯片, 微控制器, 32位, POWER, 400MHZ, MAPBGA-473
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P3P9
技术参数、封装参数在P5
应用领域在P18
导航目录
MPC8308CVMAGDA数据手册
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of 36 Go
若手册格式错乱，请下载阅览PDF原文件
Communicating via HDLC over a TDM Interface with a QUICC Engine™ UCC, Rev. 0
2 Freescale Semiconductor
Introduction
1 Introduction
The Freescale QUICC Engine block is a high-performance multiprotocol processing block available in
many microprocessor devices. Because of the many different protocols and interfaces that the QUICC
Engine block supports, it has a high degree of programmability. Depending on the protocol and interface
required for an application, the number of sub-blocks used and the amount of initialization required can
be significant. However, once initialized, the QUICC Engine block handles most of the protocol work,
freeing the CPU to handle higher level tasks.
QUICC Engine communication channels are commonly used as an HDLC controller using a time slot on
a TDM interface such as a T1 or E1 line. The following subsections provide the basic information required
to configure a QUICC Engine block-enabled device for this application.
To demonstrate how an HDLC channel can be used over TDM on an MPC8360, a software demonstration
example accompanies this applications note. As later sections introduce the sub-blocks of the QUICC
Engine block, descriptions of how the example code configures and uses the sub-blocks are also provided.
The software itself is both included in Appendix A of this document and available as a Freescale
CodeWarrior project in an accompanying download.
1.1 Introduction to the MPC8360E
Figure 1 provides a block diagram of the MPC8360E. The MPC8360E consists of three main functional
blocks: an e300c1 Power Architecture™ core, a system interface unit (SIU), and the QUICC Engine block.
The e300 core is the main CPU of the system and is responsible for running all user code. The
demonstration code provided in this application note runs on the e300 core. The system interface unit
provides the memory interfaces and system glue logic required to create a complete system on a chip.
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