Datasheet 搜索 > 微处理器 > NXP（恩智浦） > MPC8308CVMAGDA 数据手册 > MPC8308CVMAGDA 其他数据使用手册 3/36 页
￥ 7.179
MPC8308CVMAGDA 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-473
描述:
NXP MPC8308CVMAGDA 芯片, 微控制器, 32位, POWER, 400MHZ, MAPBGA-473
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P3P9
技术参数、封装参数在P5
应用领域在P18
导航目录
MPC8308CVMAGDA数据手册
Page:
of 36 Go
若手册格式错乱，请下载阅览PDF原文件
Communicating via HDLC over a TDM Interface with a QUICC Engine™ UCC, Rev. 0
Freescale Semiconductor 3
Introduction
Although a detailed understanding of both the e300 core and system interface unit are required for use of
the MPC8360, the focus of this applications note is on the QUICC Engine block.
Figure 1. MPC8360E Block Diagram
Note that other QUICC Engine block-based devices from Freescale have a similar architecture, with
different CPU cores and/or speed options, different system interface options, and different QUICC Engine
block performance and I/O options.
1.2 Review of TDM and HDLC
A time division multiplexed (TDM) bus is commonly used in telecommunication systems. A T1 line is a
type of TDM interface developed for digital transmission of voice between telephone switching offices in
Memory Controllers
GPCM/UPM/SDRAM
32/64 DDR2 Interface Unit
PCI Bridge
Local Bus
Bus Arbitration
DUART
Dual I2C
4 Channel DMA
Interrupt Controller
Protection & Configuration
System Reset
Clock Synthesizer
System Interface Unit
(SIU)
Local Bus
Baud Rate
Generators
48 KB Multiuser RAM
Interrupt Controller
UCC8
Timers
Accelerators
Dual 32-bit RISC CP
Serial DMA
2 GMII/
RGMII/TBI/RTBI
8 MII/
RMII/NMSI
8 TDM Ports
2 UTOPIA/POS-PHY
(MPHY 124 Ports)
Parallel I/O
QUICC Engine™ Block
JTAG/COP
Power
Management
Timers
FPU
Classic G2 MMUs
32 KB
D-Cache
32 KB
I-Cache
Security Engine
e300c1 Core
PCI
DDRC1
UCC7
UCC6
UCC5
UCC4
UCC3
UCC2
UCC1
MCC
USB
SPI2
Time Slot Assigner
DDRC2
SPI1
32 DDR2 Interface Unit
48 KB Instruction RAM
Parallel I/O
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
