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MPC8308CVMAGDA 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-473
描述:
NXP MPC8308CVMAGDA 芯片, 微控制器, 32位, POWER, 400MHZ, MAPBGA-473
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原理图在P3P9
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应用领域在P18
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MPC8308CVMAGDA数据手册
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Communicating via HDLC over a TDM Interface with a QUICC Engine™ UCC, Rev. 0
Freescale Semiconductor 5
QUICC Engine Sub-blocks Needed for a Single Channel of HDLC over TDM
In a T1 line, the control channel is sometimes managed directly by the framer device. When using such a
device, the TDM interface in the MPC8360E should be programmed to skip the framing bit. If the
application requires that the MPC8360E terminate the control channel, the TDM interface can be
programmed to route the framing bit to the appropriate resource inside the QUICC Engine block.
1.3 Required Documentation
At the time of this writing, the following documents were the most current MPC8360 documentation.
Please consult these for further details. For your convenience, the document order numbers are included
in parentheses. Please consult the Freescale website for updated documents or errata.
Note that the information about the QUICC Engine block in the separate QEIWRM manual supersedes the
information in the MPC8360RM.
• MPC8360 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual,
revision 2 (MPC8360ERM)
• QUICC Engine™ Block Reference Manual with Protocol Interworking, revision 2 (QEIWRM)
• MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware
Specifications, revision 2 (MPC8360EEC)
2 QUICC Engine Sub-blocks Needed for a Single Channel
of HDLC over TDM
Part of the complexity of using the QUICC Engine block stems from the many different sub-blocks
involved in a particular application. However, this complexity is primarily limited to the initialization steps
needed to setup a protocol. Once running, the QUICC Engine block handles much of the protocol
processing leaving the CPU to handle higher-level tasks.
The QUICC Engine block bundles together a microcoded communications processing block with the
necessary hardware to implement a variety of communication protocols. Within the QUICC Engine block,
the sub-blocks relevant to this note are the communications processing block, baud rate generators, time
slot assigner, and unified communication controllers (UCCs).
Note that this applications note is focused on terminating a single channel of HDLC traffic on a single
UCC. If more channels are needed, multiple UCCs can be used. However, if the number of HDLC
channels is large, the QUICC Engine has a multichannel controller (MCC) designed to handle up to 256
channels of HDLC traffic. Refer to the QEIWRM for more details on the MCC. The sections of this note
describing the time slot assigner will be helpful to the MCC user.
The communications processing sub-block is the core of the QUICC Engine block. In the MPC8360E, it
consists of two RISC communication processors (CP). Other QUICC Engine devices use different
numbers of RISC cores to provide different levels of protocol processing performance. The RISC CPs run
in real time using code from an on-chip ROM. e300 core software interacts with the CPs via shared
memory that appears in the core’s memory map. The CP sub-block is documented in the “Configuration”
chapter of the QEIWRM. The complete MPC8360 memory map is documented in the “Memory Map”
chapter of the MPC8360RM.
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