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器件3D模型￥ 1519.302
MPC8349EVVAJFB 产品描述及参数 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-672
描述:
PowerPC系列 533MHz
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
MPC8349EVVAJFB数据手册
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Instruction and Data Cache Locking on the e300 Processor Core, Rev. 1
4 Freescale Semiconductor
Disable Interrupts
4 Disable Interrupts
To ensure that interrupt service routines do not execute while the cache is loaded, which can pollute the
cache with undesired contents, all interrupts should be disabled by clearing the appropriate bits in the
machine state register (MSR) register. Table 3 lists the MSR bits that must be cleared to ensure that
interrupts are disabled.
The following assembly code disables all interrupts:
# Clear the following bits from the MSR:
# EE (16) ME (19)
# FE0 (20) FE1 (23)
mfmsr r1
lis r2, 0xffff
ori r2, r2, 0x66ff
and r1, r1, r2
mtmsr r1
sync
5 Invalidate the Caches
This section describes the invalidation of the instruction and data caches.
5.1 Instruction Cache
The entire instruction cache for the e300 microprocessor is invalidated through the instruction cache flash
invalidate bit HID0[ICFI], bit 20. Setting HID0[ICFI] and then immediately clearing it causes the entire
instruction cache to be invalidated. The following assembly code invalidates the entire instruction cache:
# Set and then clear the HIDO[ICFI] bit, bit 20
mfspr r1, HID0
mr r2, r1
ori r1, r1, 0x0800
mtspr HID0, r1
mtspr HID0, r2
sync
Table 3. MSR Bits for Disabling Interrupts
Bit Name Description
16 EE External interrupt enable
19 ME Machine check enable
20 FE0
1
1
The floating-point exception does not need to be disabled because the code that performs
cache locking does not execute floating -point operations.
Floating-point exception mode 0
23 FE1
1
Floating-point exception mode 1
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