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器件3D模型￥ 1520.592
MPC8349EVVAJFB 产品描述及参数 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-672
描述:
PowerPC系列 533MHz
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
MPC8349EVVAJFB数据手册
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若手册格式错乱，请下载阅览PDF原文件
Instruction and Data Cache Locking on the e300 Processor Core, Rev. 1
6 Freescale Semiconductor
Load the Caches
6.1 Preload Instructions into the Instruction Cache
Instructions are preloaded into the instruction cache by speculatively fetching the instructions to be loaded.
These instructions are speculatively fetched for execution when it is known that they are to be canceled.
Although the execution of instructions is canceled, the instructions remain valid in the instruction cache.
Because instructions are intentionally executed speculatively, care must be taken to ensure that all I/O
memory is marked guarded. Otherwise, speculative loads and stores to I/O space can cause data loss. (For
a full discussion of guarded memory, see PowerPC Microprocessor Family: The Programming
Environments for 32-Bit Microprocessors). The code that prefetches must be in cache-inhibited memory
as shown in the following example:
# Assuming interrupts are turned off, cache is flushed,
# the MMU is on, and we are executing in a cache-inhibited
# location in memory
# LR and r6 = Starting address of code to lock
# CTR = Number of cache blocks to lock
# r2 = nonzero numerator and denominator
# ‘loop’ must begin on an 8-byte boundary to ensure that
# the divw and beqlr+ are fetched on the same cycle.
.orig 0xFFF04000
loop: divw. r2, r2, r2 # LONG divide w/ nonzero result
beqlr+ # Cause the prefetch to happen
addi r6, r6, 32 # Find next block to prefetch
mtlr r6 # set the next block
bdnz- loop # Decrement the counter and
# branch if CTR != 0
In this example, both the divw. and beqlr+ instructions are fetched at the same time because of their
placement on a (double-word) boundary. A 64-bit coherent system bus (CSB) data bus is assumed. The
preloading code does not work for a 32-bit data bus. The divide instruction is chosen because it takes many
cycles to execute. During the divide execution, the processor starts fetching instructions speculatively at
the target destination of the branch instruction. The speculation occurs because the branch is statically
predicted as taken. This speculative fetching causes the cache block to which the link register (LR) points
to be loaded into the cache. Because the divw. instruction always produces a non-zero result, the beqlr+
is not taken, and all speculatively fetched instructions that begin execution are canceled. However, the
instructions remain valid in the cache.
If the destination instruction stream contains an unconditional branch to another memory location, the
destination of the unconditional branch instruction can also be prefetched. This does not cause a problem
if the destination of the unconditional branch is also inside the area of memory to be preloaded. However,
if the destination of the unconditional branch is not in the area of memory to be loaded, care must be taken
to ensure that the branch destination is to an area of memory that is cache inhibited. Otherwise,
unintentional instructions may be locked in the cache and the desired instructions may not be in their
expected way within the cache.
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