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CDCLVD110 用户编程技术手册 - TI（德州仪器）
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TI（德州仪器）
描述:
具有最低时钟失真斜率最高 900MHz 的 1 至 10 LVDS 时钟缓冲器
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CDCLVD110数据手册
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APPLICATION INFORMATION
Fall-Safe Information
LVDS Receiver Input Termination
Control Inputs Termination
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
For V
DD
= 0 V (power-down mode) the CDCLVD110 has fail-safe input and output pins. In power-on mode,
fail-safe biasing at input pins can be accomplished with a 10-k Ω pullup resistor from CLK0/CLK1 to VDD and a
10-k Ω pulldown resistor from CLK0/ CLK1 to GND.
The LVDS receiver inputs need to have 100- Ω termination resistors placed as close as possible across the input
pins.
No external termination is required. The CK control input has an internal 120-k. pullup resistor while SI- and
EN-control inputs each have an internal 120-k Ω pulldown resistor. If the control pins are left open per the default,
all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled.
6 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
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