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D45H11G
¥ 4.662
导航目录
  • 封装尺寸在P7
  • 型号编码规则在P1
  • 功能描述在P1P9
  • 技术参数、封装参数在P1P2P9
  • 应用领域在P1
D45H11G数据手册
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若手册格式错乱,请下载阅览PDF原文件
SiHH11N60E
www.vishay.com
Vishay Siliconix
S15-2031-Rev. A, 24-Aug-15
6
Document Number: 91651
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 18 - Basic Gate Charge Waveform
Fig. 19 - Gate Charge Test Circuit
Fig. 20 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91651
.
Q
GS
Q
GD
Q
G
V
G
Charge
10 V
D.U.T.
3 mA
V
GS
V
DS
I
G
I
D
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
P.W.
Period
dI/dt
Diode recovery
dV/dt
Ripple 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
V
GS
= 10 V
a
I
SD
Driver gate drive
D.U.T. l
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
V
DD
dV/dt controlled by R
g
Driver same type as D.U.T.
I
SD
controlled by duty factor “D”
D.U.T. - device under test
D.U.T.
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
R
g
Note
a. V
GS
= 5 V for logic level devices
V
DD

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